1.4 Digital Logic Gates and Component Identification

AEA Certified Aircraft Electronics Technician CAET

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1 Chapter 1: Basic Electrical Theory & Systems

1.1 Ohm's Law, Power, and DC Circuit Analysis 1.2 AC Fundamentals, Reactance, and Impedance 1.3 Semiconductor Devices and Power Regulation 1.4 Digital Logic Gates and Component Identification 1.5 Aircraft Electrical Power Systems: Batteries, Generation, Buses, and Circuit Protection

2 Chapter 2: CNS — Communication, Navigation & Surveillance Systems

2.1 Aviation VHF Communications and Audio Integration 2.2 Terrestrial Radio Navigation: VOR, Localizer, and Glideslope 2.3 Pulse Navigation and Surveillance: DME, Transponders, and Weather Radar 2.4 Satellite Navigation, ADS-B, and Traffic Surveillance

3 Chapter 3: Aircraft Wiring, Hardware & Installation

3.1 Aircraft Wire Selection, Sizing, and Stripping Standards 3.2 Terminations, Crimping, and Environmental Splicing 3.3 Harness Fabrication, Routing, and Lacing Standards 3.4 Shielding, Grounding, Bonding, and Antenna Installation

4 Chapter 4: Maintenance Procedures & Regulatory Requirements

4.1 14 CFR Part 43 Maintenance Records and Return to Service 4.2 Airworthiness Directives, Certifications, and Parts Traceability 4.3 Instructions for Continued Airworthiness and Systematic Troubleshooting

5 Chapter 5: Flight Instrument & Pitot-Static Systems

5.1 Pitot-Static Principles, Plumbing, and Analog Instruments 5.2 14 CFR 91.411 and 91.413 Mandatory 24-Month Testing 5.3 Gyroscopic Principles, AHRS, and Electronic Flight Displays

6 Chapter 6: Digital Databus Systems

6.1 ARINC 429 Specification, Word Layout, and Physical Signaling 6.2 Controller Area Network (CAN) and Garmin HSDB Architectures 6.3 ARINC 664/AFDX and MIL-STD-1553 Avionics Architectures

7 Chapter 7: Tools, Test Equipment & Measurement Techniques

7.1 Multimeters, Insulation Resistance Testers, and Hand Tools 7.2 Oscilloscopes, Signal Integrity, and Time-Domain Reflectometry 7.3 Avionics Ramp Test Sets and Flight Line Validation

8 Chapter 8: Safety, Housekeeping & Best Practices

8.1 Electrical Safety, Lockout/Tagout, and RF Radiation Hazards 8.2 Electrostatic Discharge (ESD) Protection and FOD Prevention 8.3 Aviation Human Factors and the Maintenance Dirty Dozen

1.4 Digital Logic Gates and Component Identification

Key Takeaways Explain This Topic AI

Digital avionics systems operate on binary discrete states (Logic 0 and Logic 1) categorized by standardized voltage thresholds, such as 5V TTL (High > 2.0V, Low < 0.8V) with an indeterminate noise region between 0.8V and 2.0V.

Primary digital logic gates include AND, OR, NOT, NAND, NOR, XOR, and XNOR; NAND and NOR gates are universal gates capable of synthesizing any Boolean logic function.

Avionics interlocking safety logic combines digital gates to automate safety functions, such as the landing gear warning horn interlock and the Weight-on-Wheels (WOW) squat switch system.

Standard resistors are identified by 4-band and 5-band color codes following Black (0) through White (9), with multiplier bands and tolerance ratings (Gold ±5%, Silver ±10%, Brown ±1%).

Aircraft wiring schematics illustrate circuit logic, whereas wiring diagrams show physical wire identification codes, gauges, connector designations (P/J), and ground studs; AC 43.13-1B calls for wire ID marks at each end and at 15-inch maximum intervals.

Last updated: October 2026

1.4 Digital Logic Gates and Component Identification

Quick Answer: Modern digital avionics units—such as Flight Management Systems (FMS), air data computers, and warning logic modules—process binary information represented by two discrete voltage states: Logic 1 (HIGH) and Logic 0 (LOW) . Standard 5V Transistor-Transistor Logic (TTL) defines a valid LOW as 0.0 V 0.0\text{ V} 0.0 V to 0.8 V 0.8\text{ V} 0.8 V and a valid HIGH as 2.0 V 2.0\text{ V} 2.0 V to 5.0 V 5.0\text{ V} 5.0 V , with the range between 0.8 V 0.8\text{ V} 0.8 V and 2.0 V 2.0\text{ V} 2.0 V representing a forbidden indeterminate zone. Avionics safety interlocks employ fundamental logic gates (AND, OR, NOT, NAND, NOR, XOR, XNOR) to process flight status discretes; for example, the landing gear warning horn triggers via Gear Locked ‾ ⋅ ( Throttle Retarded + Flaps Extended ) \overline{\text{Gear Locked}} \cdot (\text{Throttle Retarded} + \text{Flaps Extended}) Gear Locked ⋅ ( Throttle Retarded + Flaps Extended ) . Passive components are identified using standard 4-band and 5-band EIA color codes (Black 0 to White 9, Gold 5% tolerance). Aircraft wiring diagrams provide exact point-to-point pin connections, connector P/J numbers, and wire bundle identification codes conforming to FAA AC 43.13-1B.

Binary Numbering and Digital Voltage Thresholds

Unlike analog avionics that process continuously variable voltages, digital avionics compute using the binary numbering system (base-2), which comprises only two discrete digits: 0 and 1 (bits). Eight bits constitute a byte , and groups of 16 or 32 bits form avionics digital databus words (e.g., ARINC 429).

Logic Voltage Thresholds: TTL vs. CMOS

In physical microelectronics, binary states are represented by voltage ranges. Two primary logic families predominate in aircraft electronics:

5V Transistor-Transistor Logic (TTL):

Input LOW ( V I L V_{IL} V I L ): 0.0 V 0.0\text{ V} 0.0 V to 0.8 V 0.8\text{ V} 0.8 V (Guaranteed Logic 0).

Input HIGH ( V I H V_{IH} V I H ): 2.0 V 2.0\text{ V} 2.0 V to 5.0 V 5.0\text{ V} 5.0 V (Guaranteed Logic 1).

Indeterminate / Forbidden Zone: 0.8 V 0.8\text{ V} 0.8 V to 2.0 V 2.0\text{ V} 2.0 V . In this middle zone, logic gate inputs float unpredictably between states, causing circuit oscillation or erratic outputs.

3.3V Complementary Metal-Oxide-Semiconductor (CMOS):

Input LOW ( V I L V_{IL} V I L ): 0.0 V 0.0\text{ V} 0.0 V to 0.3 × V D D 0.3 \times V_{DD} 0.3 × V DD (approx. 0.0 V 0.0\text{ V} 0.0 V to 1.0 V 1.0\text{ V} 1.0 V ).

Input HIGH ( V I H V_{IH} V I H ): 0.7 × V D D 0.7 \times V_{DD} 0.7 × V DD to 3.3 V 3.3\text{ V} 3.3 V (approx. 2.3 V 2.3\text{ V} 2.3 V to 3.3 V 3.3\text{ V} 3.3 V ).

Floating Inputs and Pull-Up/Pull-Down Resistors

Because an unconnected digital input can easily float into the indeterminate threshold due to electrostatic noise and electromagnetic interference (EMI), avionics circuits incorporate pull-up or pull-down resistors (typically 4.7 k Ω 4.7\text{ k}\Omega 4.7 k Ω to 10 k Ω 10\text{ k}\Omega 10 k Ω ). A pull-up resistor connects an input line to the positive logic rail, ensuring a solid Logic 1 until an external mechanical switch or open-collector transistor pulls the line to ground (Logic 0).

Digital Logic Gates and Truth Tables

Digital logic gates perform elementary logical operations on one or more binary inputs to generate a single binary output. The seven primary gates are summarized below:

1. AND Gate

An AND gate produces a Logic 1 output only if all inputs are Logic 1 . If any input is 0, the output is 0. Boolean expression: Y = A ⋅ B Y = A \cdot B Y = A ⋅ B (or Y = A B Y = AB Y = A B ).

2. OR Gate

An OR gate produces a Logic 1 output if any input is Logic 1 . The output is 0 only when all inputs are 0. Boolean expression: Y = A + B Y = A + B Y = A + B .

3. NOT Gate (Inverter)

A NOT gate has a single input and inverts its state. If the input is 0, output is 1; if input is 1, output is 0. An inversion circle (bubble) designates the NOT function. Boolean expression: Y = A ‾ Y = \overline{A} Y = A .

4. NAND Gate

A NAND (NOT-AND) gate is an AND gate followed by an inverter. The output is 0 only when all inputs are 1 . For all other input combinations, the output is 1. Boolean expression: Y = A ⋅ B ‾ Y = \overline{A \cdot B} Y = A ⋅ B . NAND is a universal gate ; any digital logic function can be synthesized using NAND gates alone.

5. NOR Gate

A NOR (NOT-OR) gate is an OR gate followed by an inverter. The output is 1 only when all inputs are 0 . If any input is 1, output is 0. Boolean expression: Y = A + B ‾ Y = \overline{A + B} Y = A + B . NOR is also a universal gate.

6. XOR Gate (Exclusive-OR)

An XOR gate produces a Logic 1 output when the inputs are different . If both inputs are identical (both 0 or both 1), the output is 0. Boolean expression: Y = A ⊕ B = A B ‾ + A ‾ B Y = A \oplus B = A\overline{B} + \overline{A}B Y = A ⊕ B = A B + A B . XOR gates are universally employed in digital databus parity bit generation and checking.

7. XNOR Gate (Exclusive-NOR / Equivalence)

An XNOR gate is an XOR gate followed by an inverter. The output is 1 when the inputs are identical (both 0 or both 1). If the inputs are different, the output is 0. Boolean expression: Y = A ⊕ B ‾ = A B + A ‾ B ‾ Y = \overline{A \oplus B} = AB + \overline{A}\,\overline{B} Y = A ⊕ B = A B + A B .

Input A Input B AND ( A ⋅ B A \cdot B A ⋅ B ) OR ( A + B A + B A + B ) NAND ( A B ‾ \overline{AB} A B ) NOR ( A + B ‾ \overline{A+B} A + B ) XOR ( A ⊕ B A \oplus B A ⊕ B ) XNOR ( A ⊕ B ‾ \overline{A \oplus B} A ⊕ B )

0 0 0 0 1 1 0 1
0 1 0 1 1 0 1 0
1 0 0 1 1 0 1 0
1 1 1 1 0 0 0 1
Avionics Interlocking Safety Logic Applications

Digital logic gates form the core architecture of aircraft safety interlock modules, automating flight deck warnings and system protections.

1. Landing Gear Warning Horn Interlock

To prevent gear-up landing accidents, aircraft incorporate an audio warning horn that alerts the flight crew if the aircraft is configured for landing while the landing gear is not safely extended and locked.

Condition Inputs:

Landing Gear Down and Locked switch: 1 = Locked Down 1 = \text{Locked Down} 1 = Locked Down , 0 = Unsafe / In Transit / Retracted 0 = \text{Unsafe / In Transit / Retracted} 0 = Unsafe / In Transit / Retracted .

Throttle Position switch: 1 = Retarded below flight idle 1 = \text{Retarded below flight idle} 1 = Retarded below flight idle , 0 = High cruise/climb power 0 = \text{High cruise/climb power} 0 = High cruise/climb power .

Flap Position switch: 1 = Flaps extended beyond landing setting (e.g., > 25 ∘ ) 1 = \text{Flaps extended beyond landing setting (e.g., } > 25^\circ\text{)} 1 = Flaps extended beyond landing setting (e.g., > 2 5 ∘ ) , 0 = Flaps cruise setting 0 = \text{Flaps cruise setting} 0 = Flaps cruise setting .

Logic Architecture:

The throttle retarded discrete and the flap extended discrete feed a two-input OR gate . If either flight condition is true, the OR gate outputs Logic 1.

The gear-down discrete passes through an inverter (NOT gate) , converting a gear-unsafe condition ( 0 0 0 ) into an active Logic 1.

The inverted gear signal and the output of the OR gate feed a two-input AND gate .

The AND gate output drives the master warning horn audio tone generator.

Horn Alert = Gear Locked ‾ ⋅ ( Throttle Retarded + Flaps Extended ) \text{Horn Alert} = \overline{\text{Gear Locked}} \cdot (\text{Throttle Retarded} + \text{Flaps Extended}) Horn Alert = Gear Locked ⋅ ( Throttle Retarded + Flaps Extended )

If the gear is down and locked (Gear = 1), the inverted signal is 0, completely inhibiting the AND gate and keeping the horn silent regardless of throttle or flap settings.

2. Weight-on-Wheels (WOW) / Squat Switch Logic

Aircraft main landing gear oleo struts carry squat switches that actuate mechanically when aircraft weight compresses the strut upon touchdown:

Ground Mode (WOW = 1): Strut compressed. Logic interlocks:

Inhibit landing gear retraction handle solenoid (physically preventing gear lever movement on ramp).

Arm thrust reverser deployment logic.

Inhibit airborne weather radar microwave transmission to protect ground personnel.

Enable ground-only maintenance and test functions that are locked out in flight (the exact list is aircraft-specific).

Flight Mode (WOW = 0): Strut extended in air. Logic interlocks:

Enable landing gear retraction.

Lock out ground thrust reversers.

Enable airborne radar transmission.

Resistor Color Code Decoding (4-Band and 5-Band)

Fixed composition and metal-film resistors are marked with standardized colored bands developed by the Electronic Industries Alliance (EIA).

The Standard Color Mnemonic

Resistor colors correspond to numerical digits 0 through 9: Black (0), Brown (1), Red (2), Orange (3), Yellow (4), Green (5), Blue (6), Violet (7), Gray (8), White (9) .

Multiplier and tolerance bands include Gold and Silver :

Gold: Multiplier × 0.1 \times 0.1 × 0.1 ( 10 − 1 10^{-1} 1 0 − 1 ), Tolerance ± 5 % \pm 5\% ± 5% .

Silver: Multiplier × 0.01 \times 0.01 × 0.01 ( 10 − 2 10^{-2} 1 0 − 2 ), Tolerance ± 10 % \pm 10\% ± 10% .

Brown (Tolerance): ± 1 % \pm 1\% ± 1% (standard precision).

Red (Tolerance): ± 2 % \pm 2\% ± 2% .

4-Band Resistor Decoding

Band 1: First significant digit.

Band 2: Second significant digit.

Band 3: Decimal multiplier ( 10 n 10^n 1 0 n ).

Band 4: Tolerance percentage (separated by a wider physical gap).

Worked Example 1: A resistor exhibits bands Yellow - Violet - Orange - Gold :

Yellow = 4 4 4
Violet = 7 7 7
Orange = × 10 3 = × 1,000 \times 10^3 = \times 1{,}000 × 1 0 3 = × 1 , 000
Gold = ± 5 % \pm 5\% ± 5%

Nominal Resistance: 47 × 1,000 Ω = 47 k Ω 47 \times 1{,}000\ \Omega = \mathbf{47\text{ k}\Omega} 47 × 1 , 000 Ω = 47 k Ω .

Allowable Range: 47,000 ± 5 % ( ± 2,350 Ω ) = 44,650 Ω to 49,350 Ω 47{,}000 \pm 5\% (\pm 2{,}350\ \Omega) = \mathbf{44{,}650\ \Omega \text{ to } 49{,}350\ \Omega} 47 , 000 ± 5% ( ± 2 , 350 Ω ) = 44 , 650 Ω to 49 , 350 Ω .

Worked Example 2: A resistor exhibits bands Orange - White - Brown - Gold :

Orange = 3 3 3
White = 9 9 9
Brown = × 10 1 = × 10 \times 10^1 = \times 10 × 1 0 1 = × 10
Gold = ± 5 % \pm 5\% ± 5%

Nominal Resistance: 39 × 10 Ω = 390 Ω ± 5 % 39 \times 10\ \Omega = \mathbf{390\ \Omega \pm 5\%} 39 × 10 Ω = 390 Ω ± 5% ( 370.5 Ω to 409.5 Ω 370.5\ \Omega \text{ to } 409.5\ \Omega 370.5 Ω to 409.5 Ω ).

5-Band Precision Resistor Decoding

Precision metal-film avionics resistors utilize 5 bands:

Band 1: First significant digit.

Band 2: Second significant digit.

Band 3: Third significant digit.

Band 4: Decimal multiplier ( 10 n 10^n 1 0 n ).

Band 5: Tolerance rating.

Worked Precision Example: Bands Brown - Black - Black - Brown - Brown :

Digit 1 = 1 1 1 , Digit 2 = 0 0 0 , Digit 3 = 0 0 0
Multiplier = × 10 1 = × 10 \times 10^1 = \times 10 × 1 0 1 = × 10
Tolerance = ± 1 % \pm 1\% ± 1% (Brown)

Resistance: 100 × 10 = 1,000 Ω = 1.00 k Ω ± 1 % 100 \times 10 = \mathbf{1{,}000\ \Omega = 1.00\text{ k}\Omega \pm 1\%} 100 × 10 = 1 , 000 Ω = 1.00 k Ω ± 1% .

Color Digit Value Multiplier ( 10 n 10^n 1 0 n ) Tolerance Band
Black 0 × 10 0 = 1 \times 10^0 = 1 × 1 0 0 = 1 —
Brown 1 × 10 1 = 10 \times 10^1 = 10 × 1 0 1 = 10 ± 1 % \pm 1\% ± 1%
Red 2 × 10 2 = 100 \times 10^2 = 100 × 1 0 2 = 100 ± 2 % \pm 2\% ± 2%
Orange 3 × 10 3 = 1 k Ω \times 10^3 = 1\text{ k}\Omega × 1 0 3 = 1 k Ω —
Yellow 4 × 10 4 = 10 k Ω \times 10^4 = 10\text{ k}\Omega × 1 0 4 = 10 k Ω —
Green 5 × 10 5 = 100 k Ω \times 10^5 = 100\text{ k}\Omega × 1 0 5 = 100 k Ω ± 0.5 % \pm 0.5\% ± 0.5%
Blue 6 × 10 6 = 1 M Ω \times 10^6 = 1\text{ M}\Omega × 1 0 6 = 1 M Ω ± 0.25 % \pm 0.25\% ± 0.25%
Violet 7 × 10 7 = 10 M Ω \times 10^7 = 10\text{ M}\Omega × 1 0 7 = 10 M Ω ± 0.1 % \pm 0.1\% ± 0.1%
Gray 8 × 10 8 \times 10^8 × 1 0 8 ± 0.05 % \pm 0.05\% ± 0.05%
White 9 × 10 9 \times 10^9 × 1 0 9 —
Gold — × 0.1 \times 0.1 × 0.1 ± 5 % \pm 5\% ± 5%
Silver — × 0.01 \times 0.01 × 0.01 ± 10 % \pm 10\% ± 10%
Schematic Symbols and Aircraft Wiring Conventions

An avionics technician routinely consults three distinct types of technical drawings:

Block Diagrams: High-level system architecture illustrating LRU functional interconnections without showing internal circuitry or wire pinouts.

Schematic Diagrams: Detailed electrical engineering drawings depicting theoretical circuit logic, electronic components (diodes, transistors, logic gates, relays), and signal flow from inputs (left) to outputs (right), independent of physical geometry.

Wiring Diagrams: Practical airframe installation drawings showing exact physical wiring, wire bundle harness routing, connector part numbers, terminal junction blocks, wire gauges, and grounding studs.

Aircraft Wiring Identification Standards

FAA AC 43.13-1B, Chapter 11, Section 16 (Wire Marking), says a wire's identification should combine letters and numbers that identify the wire, the circuit it belongs to, its gauge, and anything else needed to relate it to the wiring diagram. Direct markings go at each end of the wire and at 15-inch maximum intervals along it. Wires shorter than 3 inches need no marking, and wires 3 to 7 inches long are marked near the center. Printed identification sleeves, when used instead, go at each end and at intervals no longer than 6 feet.

The AC's own example of a directly marked wire is H215A20 :

H (circuit function letter): identifies the type of circuit.

215 (wire number): the unique number of that wire within the circuit.

A (wire segment letter): distinguishes segments of the same wire separated by connectors or splices.

20 (wire gauge): 20 AWG.

In the MIL-W-5088 scheme (now SAE AS50881), a suffix such as N marks a ground wire, phase letters (A, B, C) identify AC phases, and some codes start with a unit number. Many airframe manufacturers use their own codes, often built around ATA chapter numbers, so always decode a wire with that aircraft's wiring diagram manual.

Connector and Terminal Designations

P (Plug): Movable half of a multi-pin cannon connector assembly, typically terminating a wire harness bundle (e.g., P101 ).

J (Jack / Receptacle): Stationary connector receptacle mounted directly to an LRU avionics chassis or bulkhead bracket (e.g., J101 ).

TB (Terminal Block): Barrier terminal strip providing screw post junctions for ring terminal terminations.

GD / G (Ground Stud): Dedicated structural airframe grounding post bonded to metal aircraft skin.