4.2 Phase-Locked Loops (PLLs) and Frequency Synthesisers

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4.2 Phase-Locked Loops (PLLs) and Frequency Synthesisers

Key Takeaways Explain This Topic AI

A PLL uses negative feedback to align the divided VCO signal with a stable comparison reference. In an integer- N N N synthesiser, the locked output is f out = N f osc / R f_{\text{out}}=Nf_{\text{osc}}/R f out ​ = N f osc ​ / R .

Digital phase-frequency detectors compare both phase and frequency. Their charge pumps generate UP/DOWN correction pulses for wide acquisition within the available tuning range; a delayed reset reduces dead-zone effects.

The loop filter integrates charge pump current pulses into a smooth DC tuning voltage (V_tune), setting the loop natural frequency (ω_n) and damping factor (ζ ≈ 0.707).

Loop bandwidth embodies a fundamental engineering compromise: wide bandwidth provides rapid lock times and tracks out VCO microphonics but admits reference phase noise and spurs; narrow bandwidth suppresses reference spurs but slows lock acquisition and exposes VCO phase noise.

Pulse-swallow dual-modulus prescalers (P / P+1) allow high-frequency division using slower CMOS logic, while Fractional-N synthesisers achieve sub-hertz resolution with low division ratios and reduced phase noise through Sigma-Delta (ΣΔ) modulation.

Last updated: November 2026

4.2 Phase-Locked Loops (PLLs) and Frequency Synthesisers

While a quartz crystal oscillator provides exceptional frequency stability and low phase noise, it operates at only one fixed frequency (or across a tiny "rubbering" range of a few kilohertz). Modern amateur transceivers, however, must tune continuously across dozens of megahertz with sub-hertz channel resolution while retaining the absolute accuracy and stability of an atomic or crystal reference. This capability is realized through frequency synthesis , primarily using the Phase-Locked Loop (PLL) .

PLL Fundamentals and Closed-Loop Control Theory

A Phase-Locked Loop is a closed-loop negative feedback system. In a synthesiser, it adjusts the VCO until the divided VCO signal matches the comparison reference in frequency and has a stable phase relationship to it. f_osc ->[/R]-> f_ref ->[PFD]->[CP]->[LF]->[VCO]---+--> f_out

• ^ |
• | |
• +--- f_div <-[/N]<-------+

LF is the loop filter. For a 10 MHz 10\text{ MHz} 10 MHz master reference, R = 800 R=800 R = 800 gives f ref = 12.5 kHz f_{\text{ref}}=12.5\text{ kHz} f ref ​ = 12.5 kHz . With N = 11600 N=11600 N = 11600 , the locked output is 145 MHz 145\text{ MHz} 145 MHz .

Mathematical Formulation of the Closed Loop

Near lock, use an averaged small-signal phase model in the Laplace domain. The comparison-reference phase is Φ ref ( s ) \Phi_{\text{ref}}(s) Φ ref ​ ( s ) , and the divided feedback phase is Φ out ( s ) / N \Phi_{\text{out}}(s)/N Φ out ​ ( s ) / N .

Phase Detector Transfer Gain ( K d K_d K d ​ ): Converts phase error Θ e ( s ) = Φ ref ( s ) − Φ div ( s ) \Theta_e(s) = \Phi_{\text{ref}}(s) - \Phi_{\text{div}}(s) Θ e ​ ( s ) = Φ ref ​ ( s ) − Φ div ​ ( s ) into current pulses (for a charge pump) or voltage: I cp ( s ) = K d × Θ e ( s ) = ( I CP 2 π ) Θ e ( s ) [ A/rad ] I_{\text{cp}}(s) = K_d \times \Theta_e(s) = \left( \frac{I_{\text{CP}}}{2\pi} \right) \Theta_e(s) \quad [\text{A/rad}] I cp ​ ( s ) = K d ​ × Θ e ​ ( s ) = ( 2 π I CP ​ ​ ) Θ e ​ ( s ) [ A/rad ]

Loop Filter Transfer Impedance ( Z LF ( s ) Z_{\text{LF}}(s) Z LF ​ ( s ) ): Converts the charge pump current into control voltage V tune ( s ) V_{\text{tune}}(s) V tune ​ ( s ) : V tune ( s ) = I cp ( s ) × Z LF ( s ) V_{\text{tune}}(s) = I_{\text{cp}}(s) \times Z_{\text{LF}}(s) V tune ​ ( s ) = I cp ​ ( s ) × Z LF ​ ( s )

VCO Transfer Function ( K vco K_{\text{vco}} K vco ​ ): An oscillator is an ideal integrator of frequency to phase ( ϕ ( t ) = ∫ ω ( t ) d t \phi(t) = \int \omega(t) dt ϕ ( t ) = ∫ ω ( t ) d t ). In the Laplace domain, integration is represented by 1 / s 1/s 1/ s : Φ out ( s ) = K vco s V tune ( s ) , [ K vco ] = rad / ( s ⋅ V ) \Phi_{\text{out}}(s)=\frac{K_{\text{vco}}}{s}V_{\text{tune}}(s),\qquad [K_{\text{vco}}]=\text{rad}/(\text{s}\cdot\text{V}) Φ out ​ ( s ) = s K vco ​ ​ V tune ​ ( s ) , [ K vco ​ ] = rad / ( s ⋅ V )

Feedback Divider ( 1 / N 1/N 1/ N ): Scales down the output phase: Φ div ( s ) = Φ out ( s ) N \Phi_{\text{div}}(s) = \frac{\Phi_{\text{out}}(s)}{N} Φ div ​ ( s ) = N Φ out ​ ( s ) ​

Define the loop gain, including the divider, as: G ( s ) = K d K vco Z LF ( s ) s N , H ( s ) = Φ out Φ ref = N G ( s ) 1 + G ( s ) G(s)=\frac{K_dK_{\text{vco}}Z_{\text{LF}}(s)}{sN},\qquad H(s)=\frac{\Phi_{\text{out}}}{\Phi_{\text{ref}}}=\frac{NG(s)}{1+G(s)} G ( s ) = s N K d ​ K vco ​ Z LF ​ ( s ) ​ , H ( s ) = Φ ref ​ Φ out ​ ​ = 1 + G ( s ) NG ( s ) ​

Neglecting the small high-frequency capacitor C 2 C_2 C 2 ​ , the filter has Z LF = R 1 + 1 / ( s C 1 ) Z_{\text{LF}}=R_1+1/(sC_1) Z LF ​ = R 1 ​ + 1/ ( s C 1 ​ ) . With K = K d K vco / N K=K_dK_{\text{vco}}/N K = K d ​ K vco ​ / N , this gives: H ( s ) = N 2 ζ ω n s + ω n 2 s 2 + 2 ζ ω n s + ω n 2 , ω n 2 = K C 1 , 2 ζ ω n = K R 1 H(s)=N\frac{2\zeta\omega_ns+\omega_n^2}{s^2+2\zeta\omega_ns+\omega_n^2},\quad\omega_n^2=\frac{K}{C_1},\quad2\zeta\omega_n=KR_1 H ( s ) = N s 2 + 2 ζ ω n ​ s + ω n 2 ​ 2 ζ ω n ​ s + ω n 2 ​ ​ , ω n 2 ​ = C 1 ​ K ​ , 2 ζ ω n ​ = K R 1 ​

Here ω n \omega_n ω n ​ is natural angular frequency, not generally the loop's cutoff frequency. The damping ratio ζ ≈ 0.707 \zeta\approx0.707 ζ ≈ 0.707 is a common underdamped design choice; ζ = 1 \zeta=1 ζ = 1 is critical damping. Including C 2 C_2 C 2 ​ adds another pole and requires a higher-order stability check.

• Core Functional Blocks of the Synthesiser
• 1. Reference Oscillator and Reference Divider ( ÷ R \div R ÷ R )

The reference oscillator provides the timing foundation for the entire synthesiser. In commercial and amateur equipment, this is a TCXO (Temperature Compensated Crystal Oscillator) with stability of ± 0.5 to ± 2.5 ppm \pm 0.5\text{ to }\pm 2.5\text{ ppm} ± 0.5 to ± 2.5 ppm , or an OCXO (Oven Controlled Crystal Oscillator) offering stabilities down to ± 0.01 ppm \pm 0.01\text{ ppm} ± 0.01 ppm .

A programmable digital reference divider ( ÷ R \div R ÷ R ) divides the master reference frequency ( f osc f_{\text{osc}} f osc ​ , typically 10.0 MHz 10.0\text{ MHz} 10.0 MHz or 19.2 MHz 19.2\text{ MHz} 19.2 MHz ) down to the comparison reference frequency ( f ref f_{\text{ref}} f ref ​ ): f ref = f osc R f_{\text{ref}} = \frac{f_{\text{osc}}}{R} f ref ​ = R f osc ​ ​

2. Phase-Frequency Detector (PFD) and Charge Pump

Early PLLs utilized simple analog multipliers (double-balanced Gilbert cell mixers) or digital XOR gates as phase detectors. However, these circuits suffered from narrow pull-in ranges (lock ranges of only a few kilohertz) and could falsely lock onto odd harmonics of the reference.

Modern synthesisers universally employ the digital tri-state Phase-Frequency Detector (PFD) , constructed from two D-type flip-flops and an internal reset AND gate: f_ref --> [DFF1: D=1] --> UP --> Charge-pump source

f_div --> [DFF2: D=1] --> DOWN --> Charge-pump sink

UP, DOWN --> [AND] --> [Reset delay] --> CLR1 and CLR2

Each DFF is clocked by its labelled input edge.

The delayed AND output clears both DFFs.

Tri-State Operational Modes:

State 1 (VCO lagging or lower frequency): The rising edge of f ref f_{\text{ref}} f ref ​ arrives before the edge of f div f_{\text{div}} f div ​ . The top flip-flop triggers, asserting the UP pulse high. The charge pump switches on its constant-current source ( + I CP +I_{\text{CP}} + I CP ​ ), pumping charge into the loop filter to raise V tune V_{\text{tune}} V tune ​ and increase VCO frequency.

State 2 (VCO leading or higher frequency): The rising edge of f div f_{\text{div}} f div ​ arrives first. The bottom flip-flop triggers, asserting the DOWN pulse high. The charge pump turns on its constant-current sink ( − I CP -I_{\text{CP}} − I CP ​ ), draining charge from the loop filter to lower V tune V_{\text{tune}} V tune ​ and decrease VCO frequency.

State 3 (Locked state): Nearly coincident edges produce short UP and DOWN pulses before reset. In the ideal matched pump their average currents balance. The filter holds the required tuning voltage between updates; real mismatch and leakage can produce ripple and a small phase offset.

Frequency-Sensitive Acquisition: The PFD indicates which input is faster as well as which edge leads. This guides acquisition from larger frequency errors than a phase-only detector and avoids its harmonic-lock ambiguity. Successful lock still requires the target to lie within the VCO/control range and the detector's operating limits.

The Dead-Zone Phenomenon: Very short pulses may fail to switch the charge pump reliably. An intentional reset delay produces anti-backlash pulses even near zero phase error, reducing this dead zone. Pump mismatch and switching transients still matter for phase noise and reference spurs.

3. The Loop Filter (Low-Pass Filter)

The loop filter is the electrical heart of the PLL. It performs three critical tasks:

It integrates the discrete current pulses ( + I CP / − I CP +I_{\text{CP}} / -I_{\text{CP}} + I CP ​ / − I CP ​ ) from the charge pump into a smooth, continuous analog DC tuning voltage ( V tune V_{\text{tune}} V tune ​ ).

It attenuates high-frequency reference ripple and charge pump switching transients before they can modulate the VCO.

It establishes the dynamic control loop parameters: natural frequency ( ω n \omega_n ω n ​ ), damping factor ( ζ \zeta ζ ), and phase margin.

A typical second-order passive lead-lag loop filter consists of a series resistor R 1 R_1 R 1 ​ and capacitor C 1 C_1 C 1 ​ , shunted by a smaller capacitor C 2 C_2 C 2 ​ : From Charge To VCO

• Pump Output Tuning Input
• o------------------------+--------------------------o
• | |
• -- C_2 [R_1]
• -- |
• | --- C_1
• | ---
• | |
• /// ///

C 1 C_1 C 1 ​ acts as the primary integrator, accumulating charge to set the steady-state DC voltage.

R 1 R_1 R 1 ​ introduces a zero that supplies phase lead and improves phase margin. Without it, the loop-filter capacitor and the VCO provide two ideal integrators, giving an undamped loop model. Actual stability also depends on the additional poles and delays.

C 2 C_2 C 2 ​ (typically sized at C 2 ≈ C 1 / 10 C_2 \approx C_1 / 10 C 2 ​ ≈ C 1 ​ /10 ) adds a high-frequency pole to smooth the sharp voltage steps across R 1 R_1 R 1 ​ caused by the charge pump current edges, attenuating reference ripple.

4. The Voltage-Controlled Oscillator (VCO)

The VCO is an LC oscillator whose resonant frequency is electronically tuned by varactor (varicap) diodes . When reverse-bias tuning voltage V tune V_{\text{tune}} V tune ​ increases, the varactor depletion layer widens, reducing its junction capacitance ( C v C_v C v ​ ) and increasing the oscillator frequency: f out = 1 2 π L ( C fixed + C v ( V tune ) ) f_{\text{out}} = \frac{1}{2\pi \sqrt{L (C_{\text{fixed}} + C_v(V_{\text{tune}}))}} f out ​ = 2 π L ( C fixed ​ + C v ​ ( V tune ​ )) ​ 1 ​

The sensitivity of the VCO is denoted by its tuning gain K vco K_{\text{vco}} K vco ​ , defined in megahertz per volt ( MHz/V \text{MHz/V} MHz/V ) or radians per second per volt: K vco = 2 π × Δ f Δ V tune [ rad / ( s ⋅ V ) ] K_{\text{vco}} = 2\pi \times \frac{\Delta f}{\Delta V_{\text{tune}}} \quad [\text{rad}/(\text{s}\cdot\text{V})] K vco ​ = 2 π × Δ V tune ​ Δ f ​ [ rad / ( s ⋅ V )]

Because varactor capacitance is non-linear ( C v ∝ ( V tune ) − n C_v \propto (V_{\text{tune}})^{-n} C v ​ ∝ ( V tune ​ ) − n ), K vco K_{\text{vco}} K vco ​ varies across the tuning band, requiring careful loop filter design to maintain stability across all operating frequencies.

5. Programmable Frequency Divider ( ÷ N \div N ÷ N )

The programmable frequency divider is a digital counter that decrements from a loaded binary integer N N N down to zero, outputting one pulse for every N N N input cycles from the VCO: f div = f out N f_{\text{div}} = \frac{f_{\text{out}}}{N} f div ​ = N f out ​ ​

When the loop achieves phase lock, the PFD forces f div = f ref f_{\text{div}} = f_{\text{ref}} f div ​ = f ref ​ . Consequently, the synthesised output frequency is an exact integer multiple of the reference comparison frequency: f out = N × f ref = N × ( f osc R ) f_{\text{out}} = N \times f_{\text{ref}} = N \times \left( \frac{f_{\text{osc}}}{R} \right) f out ​ = N × f ref ​ = N × ( R f osc ​ ​ )

Changing the integer N N N in the divider's control register steps the output frequency in discrete increments equal to f ref f_{\text{ref}} f ref ​ : Δ f channel = f ref \Delta f_{\text{channel}} = f_{\text{ref}} Δ f channel ​ = f ref ​

Performance Trade-Offs in PLL Synthesiser Design

Designing a high-performance amateur radio PLL synthesiser involves balancing conflicting engineering trade-offs between lock time, phase noise, channel step size, and reference spurs.

The Loop Bandwidth Compromise

The loop bandwidth B L B_L B L ​ describes the range of offset frequencies over which feedback substantially corrects the VCO. Its relation to natural frequency ω n \omega_n ω n ​ depends on damping and loop order; it separates two approximate regimes:

Inside the Loop Bandwidth: Feedback suppresses VCO noise at sufficiently low offsets. The reference phase-noise component at the PFD input is transferred to the output with approximately 20 log ⁡ 10 N 20\log_{10}N 20 lo g 10 ​ N amplification. PFD, charge-pump and divider noise also contribute, so this component alone is not the total output noise: L out,ref ( f ) ≈ L ref at PFD ( f ) + 20 log ⁡ 10 N [ dBc/Hz ] \mathcal{L}_{\text{out,ref}}(f)\approx\mathcal{L}_{\text{ref at PFD}}(f)+20\log_{10}N\quad[\text{dBc/Hz}] L out,ref ​ ( f ) ≈ L ref at PFD ​ ( f ) + 20 lo g 10 ​ N [ dBc/Hz ]

For a fixed reference-noise component, doubling N N N raises that component by 6.02 dB 6.02\text{ dB} 6.02 dB . If the same master oscillator is first divided by R R R , its net low-offset phase multiplication is N / R N/R N / R , not N N N .

Outside the Loop Bandwidth: Feedback provides progressively less correction. The free-running VCO noise usually dominates, although other circuit noise can still contribute. The transition is gradual rather than a sharp boundary.

Parameter Wider Loop Bandwidth Narrower Loop Bandwidth

Settling Generally faster for a comparable stable loop Generally slower; exact time depends on the step and tolerance

• VCO Noise Suppression Extends correction to higher offsets Exposes VCO noise at lower offsets
• Reference/PFD Noise Passed over a wider range of offsets Attenuated sooner above the loop bandwidth
• Reference Spurs Usually more difficult to filter Usually more attenuation at the comparison frequency

Stability Check phase margin, delays and sampling effects Still requires appropriate damping and pole placement

Reference Spurs

Even in a locked condition, tiny leakage currents through the charge pump switches and parasitic capacitance discharge periodically pulse the loop filter at the comparison frequency f ref f_{\text{ref}} f ref ​ . This periodic ripple modulates V tune V_{\text{tune}} V tune ​ , frequency-modulating the VCO and producing discrete sideband spikes known as reference spurs at frequency offsets of: f spur = f out ± k f ref ( k ∈ { 1 , 2 , 3 , … } ) f_{\text{spur}} = f_{\text{out}} \pm k f_{\text{ref}} \quad (k \in \{1, 2, 3, \dots\}) f spur ​ = f out ​ ± k f ref ​ ( k ∈ { 1 , 2 , 3 , … })

In a receiver, reference spurs can mix with strong adjacent-channel signals, converting them directly into the intermediate frequency (reciprocal mixing) and masking weak desired signals. Suppressing reference spurs requires ultra-low-leakage charge pump design and adding extra low-pass filtering poles (e.g. C 2 , C 3 C_2, C_3 C 2 ​ , C 3 ​ ) in the loop filter.

High-Frequency Division: Dual-Modulus Prescalers and Pulse-Swallow Counters

At VHF and UHF, a high-speed prescaler reduces the RF clock rate before the larger programmable counters. This lets the counters use slower, lower-power circuitry; the attainable RF frequency depends on the chosen IC, rather than on a universal CMOS speed limit.

To overcome this, engineers utilize a dual-modulus prescaler coupled to a pulse-swallow counter : RF -> [Prescaler P/(P+1)]---+--> [M counter] --> f_div to PFD

• ^ |
• | +--> [S counter] ---+
• | |
• +---- modulus control <-------------+

M timeout reloads both M and S and restores P+1 mode.

Dual-Modulus Prescaler ( P / P + 1 P / P+1 P / P + 1 ): A high-speed divider capable of dividing by either P P P or P + 1 P+1 P + 1 based on a logic state on its modulus control line (typical prescaler values are 32 / 33 32/33 32/33 or 64 / 65 64/65 64/65 ).

Main Counter ( M M M ) and Swallow Counter ( S S S ): Both are clocked by the prescaler output and reloaded together. For the simple cycle shown, choose 0 ≤ S < P 0\le S<P 0 ≤ S < P and S ≤ M S\le M S ≤ M , within the IC's permitted counter values.

Pulse-Swallowing Operating Cycle

At cycle start, the prescaler is set to divide by P + 1 P + 1 P + 1 . Both M M M and S S S count down from their preset values.

After S S S output pulses from the prescaler, the Swallow Counter reaches zero, halts, and flips the modulus control line to force the prescaler to divide by P P P .

The total RF cycles elapsed during this first phase is:

N 1 = S × ( P + 1 ) N_1 = S \times (P + 1) N 1 ​ = S × ( P + 1 )

The Main Counter continues counting down for the remaining ( M − S ) (M - S) ( M − S ) pulses at the divide-by- P P P rate before it reaches zero.

The total RF cycles elapsed during this second phase is:

N 2 = ( M − S ) × P N_2 = (M - S) \times P N 2 ​ = ( M − S ) × P

When the Main Counter reaches zero, it outputs a single pulse to the PFD, reloads both M M M and S S S counters, and the cycle repeats.

Summing the RF cycles over the complete sequence reveals the total effective division ratio N N N : N = N 1 + N 2 = S ( P + 1 ) + ( M − S ) P = S P + S + M P − S P = M ⋅ P + S N = N_1 + N_2 = S(P + 1) + (M - S)P = SP + S + MP - SP = M \cdot P + S N = N 1 ​ + N 2 ​ = S ( P + 1 ) + ( M − S ) P = SP + S + MP − SP = M ⋅ P + S

Varying S S S provides unit steps in N = M P + S N=MP+S N = MP + S within the legal divide range. For this ideal dual-modulus arrangement, all consecutive N ≥ P ( P − 1 ) N\ge P(P-1) N ≥ P ( P − 1 ) are representable; a particular IC may impose further counter or operating limits.

• Integer- N N N vs. Fractional- N N N Frequency Synthesisers
• The Fundamental Limitation of Integer- N N N Synthesisers

In an Integer- N N N PLL, the output channel step size is strictly equal to the reference comparison frequency ( Δ f = f ref \Delta f = f_{\text{ref}} Δ f = f ref ​ ). For narrow-band amateur modes (CW, SSB), channel steps of 10 Hz 10\text{ Hz} 10 Hz or 100 Hz 100\text{ Hz} 100 Hz are required. Setting f ref = 100 Hz f_{\text{ref}} = 100\text{ Hz} f ref ​ = 100 Hz creates severe performance bottlenecks:

To generate a 144 MHz 144\text{ MHz} 144 MHz signal with f ref = 100 Hz f_{\text{ref}} = 100\text{ Hz} f ref ​ = 100 Hz , the division ratio must be N = 144 , 000 , 000 / 100 = 1 , 440 , 000 N = 144,000,000 / 100 = 1,440,000 N = 144 , 000 , 000/100 = 1 , 440 , 000 .

The reference component at the PFD input is multiplied by 20 log ⁡ 10 ( 1 , 440 , 000 ) ≈ 123.2 dB 20\log_{10}(1,440,000)\approx123.2\text{ dB} 20 lo g 10 ​ ( 1 , 440 , 000 ) ≈ 123.2 dB . This is a transfer term, not a complete prediction of the synthesiser's phase noise.

The low comparison frequency restricts useful loop bandwidth. A bandwidth well below the comparison frequency helps limit sampling effects and ripple; settling depends on damping, frequency step and the permitted final error.

The Fractional- N N N Synthesiser Architecture

A Fractional- N N N Synthesiser breaks the rigid lock between channel step size and reference frequency. It allows the effective division ratio to take non-integer, fractional values: N eff = N + K F N_{\text{eff}} = N + \frac{K}{F} N eff ​ = N + F K ​

where N N N is the integer portion, K K K is the fractional numerator, and F F F is the fractional modulus (accumulator capacity). Average Division Ratio:

• N_eff = N + (K / F)
• +------------------------+
• f_out ------------------>| Dual-Modulus Divider |-----> f_div to PFD
• | ÷N or ÷(N+1) |
• +------------------------+
• ^
• | Carry Out (Selects ÷(N+1))
• +------------------------+
• f_ref ------------------>| Digital Accumulator |
• | (Capacity F) |
• +------------------------+
• ^
• | Frequency Word (K)

Principle of Operation: The divider alternates dynamically between dividing by N N N and N + 1 N + 1 N + 1 . For example, to divide by 10.25 10.25 10.25 , the divider divides by 10 10 10 for three reference cycles and by 11 11 11 for one cycle, producing an average division ratio of: N eff = 10 + 10 + 10 + 11 4 = 41 4 = 10.25 N_{\text{eff}} = \frac{10 + 10 + 10 + 11}{4} = \frac{41}{4} = 10.25 N eff ​ = 4 10 + 10 + 10 + 11 ​ = 4 41 ​ = 10.25

Fine Frequency Grid: The step size is Δ f = f ref / F \Delta f=f_{\text{ref}}/F Δ f = f ref ​ / F . A large modulus permits fine steps while keeping the comparison frequency high and N N N relatively low. This can improve the noise/settling trade-off, but actual performance depends on the PLL, VCO, loop filter and fractional spurs.

Fractional Spurs and Sigma-Delta ( Σ Δ \Sigma\Delta ΣΔ ) Modulation: Repeating divider sequences create periodic phase errors and spurious tones; their offsets depend on the sequence. Sigma-delta divider control preserves the required average ratio while shaping quantization noise toward higher offsets, where the loop filter provides more attenuation. It does not eliminate all fractional or integer-boundary spurs. Modulator settings, frequency planning and loop bandwidth must control both tones and shaped noise.

Comparison of Synthesiser Architectures

Feature Integer- N N N PLL Fractional- N N N PLL

Frequency Grid Steps of f ref f_{\text{ref}} f ref ​ for unit changes in N N N Steps of f ref / F f_{\text{ref}}/F f ref ​ / F

Comparison Frequency Fine steps may require a low value Fine steps can coexist with a higher value

Division Ratio f out / f ref f_{\text{out}}/f_{\text{ref}} f out ​ / f ref ​ , an integer Average ratio N + K / F N+K/F N + K / F

Phase Noise Depends on reference, PFD, divider and VCO noise A higher comparison frequency can help; quantization noise must also be controlled

Loop Bandwidth/Settling Chosen for stability and noise requirements Higher comparison frequency can permit wider bandwidth and faster settling

• Spurs Reference-related tones remain possible Reference, fractional and integer-boundary spurs remain possible
• Implementation Fixed integer division for each setting Divider control generates the desired average ratio
• Worked Engineering Calculations
• Example 1: Integer- N N N Synthesiser Design for a 2-Meter VHF Transceiver

Problem: An amateur 2 -meter 2\text{-meter} 2 -meter VHF FM transceiver covers 144.000 MHz 144.000\text{ MHz} 144.000 MHz to 148.000 MHz 148.000\text{ MHz} 148.000 MHz with a standard channel spacing of 12.5 kHz 12.5\text{ kHz} 12.5 kHz . A master 10.000 MHz 10.000\text{ MHz} 10.000 MHz TCXO reference is used. Calculate:

The required reference divider ratio ( R R R ).

The minimum and maximum programmable divider ratios ( N min N_{\text{min}} N min ​ and N max N_{\text{max}} N max ​ ).

The theoretical phase noise penalty introduced by the divider ratio at 144.000 MHz 144.000\text{ MHz} 144.000 MHz .

Solution:

Reference Divider Ratio ( R R R ): The reference comparison frequency must match channel spacing ( f ref = 12.5 kHz f_{\text{ref}} = 12.5\text{ kHz} f ref ​ = 12.5 kHz ): R = f osc f ref = 10.000 MHz 12.5 kHz = 10 , 000 , 000 Hz 12 , 500 Hz = 800 R = \frac{f_{\text{osc}}}{f_{\text{ref}}} = \frac{10.000\text{ MHz}}{12.5\text{ kHz}} = \frac{10,000,000\text{ Hz}}{12,500\text{ Hz}} = 800 R = f ref ​ f osc ​ ​ = 12.5 kHz 10.000 MHz ​ = 12 , 500 Hz 10 , 000 , 000 Hz ​ = 800

Divider Integer Values: N min = f out(min) f ref = 144.000 MHz 12.5 kHz = 144 , 000 kHz 12.5 kHz = 11 , 520 N_{\text{min}} = \frac{f_{\text{out(min)}}}{f_{\text{ref}}} = \frac{144.000\text{ MHz}}{12.5\text{ kHz}} = \frac{144,000\text{ kHz}}{12.5\text{ kHz}} = 11,520 N min ​ = f ref ​ f out(min) ​ ​ = 12.5 kHz 144.000 MHz ​ = 12.5 kHz 144 , 000 kHz ​ = 11 , 520 N max = f out(max) f ref = 148.000 MHz 12.5 kHz = 148 , 000 kHz 12.5 kHz = 11 , 840 N_{\text{max}} = \frac{f_{\text{out(max)}}}{f_{\text{ref}}} = \frac{148.000\text{ MHz}}{12.5\text{ kHz}} = \frac{148,000\text{ kHz}}{12.5\text{ kHz}} = 11,840 N max ​ = f ref ​ f out(max) ​ ​ = 12.5 kHz 148.000 MHz ​ = 12.5 kHz 148 , 000 kHz ​ = 11 , 840

Phase Noise Penalty: Δ L = 20 log ⁡ 10 ( N min ) = 20 log ⁡ 10 ( 11 , 520 ) ≈ 20 × 4.06145 ≈ 81.23 dB \Delta \mathcal{L} = 20 \log_{10}(N_{\text{min}}) = 20 \log_{10}(11,520) \approx 20 \times 4.06145 \approx 81.23\text{ dB} Δ L = 20 lo g 10 ​ ( N min ​ ) = 20 lo g 10 ​ ( 11 , 520 ) ≈ 20 × 4.06145 ≈ 81.23 dB

The reference component measured at the PFD input is multiplied by 81.23 dB 81.23\text{ dB} 81.23 dB inside the loop bandwidth. Relative to the original 10 MHz 10\text{ MHz} 10 MHz TCXO, the ideal net multiplication is N / R = 14.4 N/R=14.4 N / R = 14.4 , or 23.17 dB 23.17\text{ dB} 23.17 dB . Additional circuit noise must be included separately.

Example 2: Pulse-Swallow Prescaler Values

Problem: A UHF synthesiser uses a 32 / 33 32/33 32/33 dual-modulus prescaler ( P = 32 P = 32 P = 32 ) to synthesize f out = 432.500 MHz f_{\text{out}} = 432.500\text{ MHz} f out ​ = 432.500 MHz with a comparison frequency f ref = 25 kHz f_{\text{ref}} = 25\text{ kHz} f ref ​ = 25 kHz . Determine the required Main Counter value ( M M M ) and Swallow Counter value ( S S S ).

Solution:

Total Division Ratio ( N N N ): N = f out f ref = 432 , 500 kHz 25 kHz = 17 , 300 N = \frac{f_{\text{out}}}{f_{\text{ref}}} = \frac{432,500\text{ kHz}}{25\text{ kHz}} = 17,300 N = f ref ​ f out ​ ​ = 25 kHz 432 , 500 kHz ​ = 17 , 300

Calculating M M M and S S S using N = M ⋅ P + S N = M \cdot P + S N = M ⋅ P + S : M = ⌊ N P ⌋ = ⌊ 17 , 300 32 ⌋ = ⌊ 540.625 ⌋ = 540 M = \left\lfloor \frac{N}{P} \right\rfloor = \left\lfloor \frac{17,300}{32} \right\rfloor = \lfloor 540.625 \rfloor = 540 M = ⌊ P N ​ ⌋ = ⌊ 32 17 , 300 ​ ⌋ = ⌊ 540.625 ⌋ = 540 S = N − ( M × P ) = 17 , 300 − ( 540 × 32 ) = 17 , 300 − 17 , 280 = 20 S = N - (M \times P) = 17,300 - (540 \times 32) = 17,300 - 17,280 = 20 S = N − ( M × P ) = 17 , 300 − ( 540 × 32 ) = 17 , 300 − 17 , 280 = 20

Verify Constraints:

S = 20 < P = 32 S = 20 < P = 32 S = 20 < P = 32 (Valid: swallow counter does not exceed prescaler modulus).

S = 20 < M = 540 S = 20 < M = 540 S = 20 < M = 540 (Valid: swallow counter terminates before main counter finishes).

Result: M = 540 M = 540 M = 540 , S = 20 S = 20 S = 20 .

Example 3: Fractional Grid and Phase-Noise Transfer

Problem: Compare a 432 MHz 432\text{ MHz} 432 MHz target using (A) integer- N N N with f ref = 100 Hz f_{\text{ref}}=100\text{ Hz} f ref ​ = 100 Hz and (B) fractional- N N N with f ref = 25 MHz f_{\text{ref}}=25\text{ MHz} f ref ​ = 25 MHz and F = 2 18 = 262144 F=2^{18}=262144 F = 2 18 = 262144 . Both derive their reference from the same 25 MHz 25\text{ MHz} 25 MHz master. Assess divider ratios, frequency resolution and reference-noise transfer.

1. Integer- N N N : R A = 250000 , N A = 432000000 100 = 4320000 , 20 log ⁡ 10 N A = 132.71 dB R_A=250000,\qquad N_A=\frac{432000000}{100}=4320000,\qquad20\log_{10}N_A=132.71\text{ dB} R A ​ = 250000 , N A ​ = 100 432000000 ​ = 4320000 , 20 lo g 10 ​ N A ​ = 132.71 dB

2. Fractional- N N N frequency grid: The desired average ratio is 432 / 25 = 17.28 432/25=17.28 432/25 = 17.28 . Its fractional numerator would be 0.28 F = 73400.32 0.28F=73400.32 0.28 F = 73400.32 , which is not an integer. Choose the nearest K = 73400 K=73400 K = 73400 : f B = ( 17 + 73400 262144 ) 25000000 ≈ 431999969.48 Hz f_B=\left(17+\frac{73400}{262144}\right)25000000\approx431999969.48\text{ Hz} f B ​ = ( 17 + 262144 73400 ​ ) 25000000 ≈ 431999969.48 Hz

This is about 30.52 Hz 30.52\text{ Hz} 30.52 Hz below the target. The available step is: Δ f = 25000000 262144 ≈ 95.37 Hz \Delta f=\frac{25000000}{262144}\approx95.37\text{ Hz} Δ f = 262144 25000000 ​ ≈ 95.37 Hz

Thus the resolution is finer than 100 Hz 100\text{ Hz} 100 Hz , but neither the exact target nor every 100 Hz 100\text{ Hz} 100 Hz channel lies on this grid.

3. Reference-noise transfer: The fractional divider term is approximately 20 log ⁡ 10 ( 17.28 ) = 24.75 dB 20\log_{10}(17.28)=24.75\text{ dB} 20 lo g 10 ​ ( 17.28 ) = 24.75 dB . Subtracting it from 132.71 dB 132.71\text{ dB} 132.71 dB gives 107.96 dB 107.96\text{ dB} 107.96 dB , but this is not the output-noise improvement. The integer system's reference divider already reduces the master's phase fluctuations. For both systems, the ideal low-offset master-to-output ratio is approximately: N R = 432 MHz 25 MHz = 17.28 \frac{N}{R}=\frac{432\text{ MHz}}{25\text{ MHz}}=17.28 R N ​ = 25 MHz 432 MHz ​ = 17.28

The master's reference-noise contribution therefore has essentially the same 24.75 dB 24.75\text{ dB} 24.75 dB multiplication. A fair total-noise comparison also needs the PFD/charge-pump, divider, quantization and VCO noise with their loop responses.