3.2 Bipolar Junction Transistors, FETs, and Operational Amplifiers

ACMA Amateur Radio Advanced Recognition Certificate - Theory Exam

Track your progress as you read

Finished sections get a check mark.

1 Chapter 1: DC Theory, Circuit Laws & Passive Components

1.1 DC Circuit Analysis, Ohm's Law, and Kirchhoff's Laws 1.2 AC Fundamentals, Sine Waves, Peak, RMS, and Phase Relationships 1.3 Inductance, Capacitance, Reactance, and Time Constants

2 Chapter 2: Impedance, Resonance & Passive Filters

2.1 Complex Impedance, Phasors, and AC Circuit Analysis 2.2 Series and Parallel LC Resonance and Q Factor 2.3 Passive Filters, Cutoff Frequency, and Attenuator Pads

3 Chapter 3: Semiconductor Devices & Power Supplies

3.1 Semiconductor Diodes, Zener Regulators, and Rectifier Circuits 3.2 Bipolar Junction Transistors, FETs, and Operational Amplifiers 3.3 Thermionic Valves (Vacuum Tubes) and High-Power Linear Amplifiers 3.4 DC Power Supplies, Filter Networks, and Voltage Regulators

4 Chapter 4: Oscillators & Frequency Synthesis

4.1 RF Oscillators, LC Tank Topologies, and Frequency Stability 4.2 Phase-Locked Loops (PLLs) and Frequency Synthesisers 4.3 Direct Digital Synthesis (DDS), SDR Architectures, and Digital Filter Topologies

5 Chapter 5: RF Amplifiers & Linearity

5.1 Classes of Amplification, Conduction Angles, and Operating Efficiency 5.2 RF Power Amplifiers, Push-Pull Topologies, and Output Matching 5.3 Amplifier Stability, Neutralisation, and Intermodulation Distortion

6 Chapter 6: Modulation & Demodulation

6.1 Amplitude Modulation, Double Sideband, and Single Sideband (SSB) 6.2 Frequency Modulation, Phase Modulation, and FM Detectors 6.3 Digital Modulation Modes, Spectral Efficiency, and Weak-Signal Protocols

7 Chapter 7: Transmitters, Mixers & Receivers

7.1 RF Mixers, Frequency Translation, and Intermodulation 7.2 Transmitter Architectures, CW Keying, and Output Filtering 7.3 Superheterodyne Receiver Design, IF Selection, and Image Rejection 7.4 Receiver Performance Specifications, Dynamic Range, and Selectivity

8 Chapter 8: Transmission Lines & Waveguides

8.1 Transmission Line Characteristics, Impedance, and Velocity Factor 8.2 Standing Waves, Reflection Coefficient, SWR, and Return Loss 8.3 Resonant Line Sections, Quarter-Wave Transformers, and Stubs

9 Chapter 9: Impedance Matching & Baluns

9.1 Lumped-Element Matching Networks and Antenna Tuning Units 9.2 Baluns, Ununs, and Common-Mode Current Choking 9.3 Feedline Losses, High-SWR Stress, and Coaxial Installation Practice

10 Chapter 10: Practical Antennas & Arrays

10.1 Resonant Dipoles, Inverted-Vs, and Multiband Wire Antennas 10.2 Quarter-Wave Verticals, Ground Systems, and Radiation Efficiency 10.3 Parasitic Arrays, Yagi-Uda Antennas, and Quad Arrays 10.4 Antenna Gain, Aperture Antennas & Horns, ERP/EIRP, Radiation Patterns

11 Chapter 11: Radio Wave Propagation & Ionospheric Mechanics

11.1 Electromagnetic Wave Fundamentals, Polarisation, and Ground Waves 11.2 The Ionosphere, Solar Radiation, and Solar Cycles 11.3 Critical Frequency, Maximum Usable Frequency, and HF Propagation Paths

12 Chapter 12: VHF/UHF Propagation & Space Communications

12.1 Line-of-Sight, Tropospheric Ducting, and Diffraction 12.2 Sporadic-E, Auroral Scatter, and Trans-Equatorial Propagation 12.3 Amateur Satellites, Doppler Shift, and Earth-Moon-Earth (EME)

13 Chapter 13: Test Equipment & RF Measurements

13.1 Decibels, Power Ratios, and Cascaded Stage Calculations 13.2 RF Power Meters, Directional Couplers, and Dummy Loads 13.3 Multirange Meters, Waveform Diagnostics, Oscilloscopes, and Frequency Counters

14 Chapter 14: Advanced RF Analysis & Diagnostics

14.1 Spectrum Analyser Architecture, Operation, and Spectral Purity 14.2 Antenna Analysers, Vector Network Analysers, and Smith Charts 14.3 Calibrated Signal Generators, Grid Dip Meters, and Component Testing

15 Chapter 15: Electromagnetic Compatibility & Interference

15.1 Sources of Interference, Coupling Mechanisms, and Audio Rectification 15.2 Receiver Susceptibility, Desensitisation, and Front-End Intermodulation 15.3 Practical RFI Suppression, Filter Design, and Bonding Techniques

16 Chapter 16: Electrical, RF & Station Safety

16.1 Biological Effects of RF Energy and ARPANSA Exposure Standards 16.2 Safe Separation Distances, Power Density, and Duty Cycles 16.3 Station Electrical Safety, Battery Hazards, and Safe Headphone Use 16.4 Mast and Tower Construction, Power Line Clearance, and Lightning Protection

3.2 Bipolar Junction Transistors, FETs, and Operational Amplifiers

Key Takeaways Explain This Topic AI

BJTs are current-controlled bipolar devices stabilized against thermal runaway (-2 mV/°C V_BE shift) via voltage divider bias with emitter degeneration; FETs are unipolar, voltage-controlled devices with near-infinite input impedance.

Monolithic integrated circuits fabricate active and passive components on a shared silicon substrate, providing thermal tracking, high component density, and reduced parasitic reactances.

An ideal op-amp has infinite open-loop gain and input impedance, and zero output impedance. In linear negative-feedback operation its input voltages are equal; the inverting input is a virtual ground when the non-inverting input is grounded.

Closed-loop op-amp topologies include the inverting amplifier (V_out = -(R_f / R_in) * V_in), non-inverting amplifier (V_out = (1 + R_f / R_1) * V_in), buffer (V_out = V_in), and summing amplifier for audio mixing.

Op-amp small-signal bandwidth is approximately GBWP divided by noise gain: 1 + R_f/R_in for an inverting stage. Slew rate limits sine-wave output to f_max = SR / (2πV_p).

Last updated: November 2026

3.2 Bipolar Junction Transistors, FETs, and Operational Amplifiers

Key Focus: Active semiconductor devices and integrated circuits provide signal amplification, mixing, buffering, and filtering across amateur equipment. Mastering current-controlled BJTs, voltage-controlled FETs, monolithic planar fabrication, and operational amplifier feedback topologies is vital for the ACMA Advanced Examination.

Bipolar Junction Transistors (BJTs) and Biasing Stability

A BJT has emitter ( E E E ), base ( B B B ) and collector ( C C C ) regions. In forward-active operation, the base-emitter junction is forward biased and the collector-base junction reverse biased. For silicon, the forward junction voltage is commonly about 0.7 V at an illustrative operating current:

NPN: Base is positive relative to emitter; collector is normally above base. Conventional base/collector currents enter the device and emitter current leaves it. The emitter arrow points outward.

PNP: Bias polarities and conventional-current directions reverse: base is below emitter and collector below base. Current enters the emitter and leaves the collector/base. The emitter arrow points inward.

Using current magnitudes, I E = I B + I C I_E=I_B+I_C I E = I B + I C , β = I C / I B \beta=I_C/I_B β = I C / I B and α = β / ( β + 1 ) \alpha=\beta/(\beta+1) α = β / ( β + 1 ) . A small base-current change controls a larger collector-current change; the actual gain depends on device and operating conditions.

Fundamental BJT Configurations and Thermal Stabilization

Common Emitter (CE): Input at base, output at collector. Provides high voltage and current gain with 180 ∘ 180^\circ 18 0 ∘ phase inversion. At RF, collector-base capacitance ( C c b C_{cb} C c b ) causes capacitive feedback (the Miller effect ), limiting high-frequency bandwidth.

Common Collector (CC / Emitter Follower): Input at base, output at emitter. Delivers near-unity voltage gain ( A v ≈ 1 A_v \approx 1 A v ≈ 1 ), high input impedance, low output impedance, and zero phase shift, acting as an isolation buffer .

Common Base (CB): Input at emitter, output at collector. Provides unity current gain ( α \alpha α ), high voltage gain, and low input impedance ( 20 Ω − 50 Ω 20\ \Omega - 50\ \Omega 20 Ω − 50 Ω ). Grounding the base shields the input from the output, eliminating the Miller effect in VHF/UHF preamplifiers.

Thermal Runaway Prevention: Base-emitter forward voltage possesses a negative temperature coefficient: Δ V B E / Δ T ≈ − 2.0 mV / ∘ C \Delta V_{BE} / \Delta T \approx -2.0\text{ mV}/^\circ\text{C} Δ V BE /Δ T ≈ − 2.0 mV / ∘ C . Rising temperatures decrease V B E V_{BE} V BE , exponentially increasing I B I_B I B and I C I_C I C and risking destructive thermal runaway . Bias stability is achieved via voltage divider bias with an emitter degeneration resistor ( R E R_E R E ). The divider holds V B V_B V B constant; as temperature increases I E I_E I E , the larger drop across R E R_E R E forces V B E = V B − I E R E V_{BE} = V_B - I_E R_E V BE = V B − I E R E down, throttling base drive and stabilizing the Q Q Q -point. An AC bypass capacitor ( C E C_E C E ) across R E R_E R E prevents AC gain reduction.

Field Effect Transistors (FETs) and CMOS Architecture

Field Effect Transistors are voltage-controlled , unipolar devices: conduction occurs strictly via majority carriers flowing from Source ( S S S ) to Drain ( D D D ) through a channel modulated by the Gate ( G G G ).

Junction FET (JFET): Employs a reverse-biased gate junction. For an N-channel JFET, normal gate bias has V G S ≤ 0 V_{GS}\le0 V GS ≤ 0 ; a P-channel device uses the opposite polarity. Above pinch-off ( ∣ V p ∣ |V_p| ∣ V p ∣ ), drain current saturates at I D = I D S S ( 1 − V G S / V p ) 2 I_D = I_{DSS}(1 - V_{GS}/V_p)^2 I D = I D SS ( 1 − V GS / V p ) 2 .

MOSFETs: An ultra-thin silicon dioxide ( SiO 2 \text{SiO}_2 SiO 2 ) layer insulates the gate ( Z i n > 10 14 Ω Z_{in} > 10^{14}\ \Omega Z in > 1 0 14 Ω ), requiring ESD precautions. In depletion-mode , a channel exists at V G S = 0 V V_{GS} = 0\text{ V} V GS = 0 V ; An N-channel enhancement-mode device requires positive gate-to-source voltage above its threshold; a P-channel device requires the opposite polarity.

Dual-Gate MOSFETs: Feature two gates in series; Gate 1 receives RF while Gate 2 receives AGC bias or LO injection. Gate 2 acts as an electrostatic shield ( C g d < 0.02 pF C_{gd} < 0.02\text{ pF} C g d < 0.02 pF ), allowing gain control without detuning tuned circuits.

CMOS Technology: Pairs complementary P-channel and N-channel MOSFETs. With one transistor always off in any static state, CMOS draws near-zero static DC power , consuming energy only during switching transitions ( P = C V 2 f P = C V^2 f P = C V 2 f ).

RF Power Devices: LDMOS devices operate at 50 V 50\text{ V} 50 V rails with high gain and extreme mismatch tolerance (SWR > 65 : 1 > 65:1 > 65 : 1 ) for HF/VHF power amplifiers. GaN HEMTs exploit a wide bandgap ( 3.4 eV 3.4\text{ eV} 3.4 eV ) for high efficiency into microwave bands.

FET Amplifier Configurations

“Common” identifies the terminal held at signal reference, which need not be DC ground. For ordinary voltage-amplifier arrangements:

FET stage Signal input/output Voltage phase Input impedance Output impedance
Common source Gate / drain Inverting High Relatively high
Common gate Source / drain Non-inverting Low, roughly 1 / g m 1/g_m 1/ g m Relatively high

Common drain (source follower) Gate / source Non-inverting, gain near but below 1 High Low, roughly 1 / g m 1/g_m 1/ g m

These correspond to common-emitter, common-base and emitter-follower BJT arrangements. Bias networks, loading, feedback and frequency alter the actual impedances; gate capacitance matters at RF.

Simple Integrated Circuits (ICs)

Monolithic integrated circuits fabricate active transistors, diodes, and resistors on a single monocrystalline silicon die using planar photolithography, diffusion, and metallization.

Key Advantages:

Matched Thermal Characteristics: Nearby components on one die track temperature closely. Matched differential-pair transistors reduce input offset and its temperature drift; real ICs retain finite offset and drift.

Miniaturization & Density: Concentrates complex circuits into compact packages with minimal weight.

Reduced Parasitics: Microscopic interconnects minimize stray lead inductances and capacitances.

Linear vs Digital ICs:

Linear / Analogue ICs: Process continuous signals with proportional fidelity (e.g., op-amps, voltage regulators, RF mixers).

Digital ICs: Switch between discrete binary states (0 and 1) between saturation and cutoff (e.g., CMOS logic, microcontrollers, DDS chips).

Operational Amplifiers and the Golden Rules

An operational amplifier (op-amp) is a high-gain direct-coupled differential amplifier.

Ideal Characteristics: Infinite open-loop voltage gain ( A O L → ∞ A_{OL} \to \infty A O L → ∞ ), infinite input impedance ( Z i n → ∞ Z_{in} \to \infty Z in → ∞ ), zero output impedance ( Z o u t → 0 Z_{out} \to 0 Z o u t → 0 ), infinite bandwidth, and zero input offset voltage/drift ( V o s → 0 V_{os} \to 0 V os → 0 , Δ V o s / Δ T → 0 \Delta V_{os}/\Delta T \to 0 Δ V os /Δ T → 0 ).

The Two Golden Rules of Negative Feedback:

Rule 1: Zero current flows into either input terminal ( I + = I − = 0 I_+ = I_- = 0 I + = I − = 0 ).

Rule 2: Negative feedback drives differential input voltage to zero ( V + = V − V_+ = V_- V + = V − ). Grounding the non-inverting input ( V + = 0 V V_+ = 0\text{ V} V + = 0 V ) forces the inverting terminal to become a virtual ground ( V − = 0 V V_- = 0\text{ V} V − = 0 V ).

Standard Op-Amp Topologies and Dynamic Limitations

Inverting Amplifier: Input connects through R i n R_{in} R in to the inverting input with feedback resistor R f R_f R f . With the inverting terminal at virtual ground: V o u t = − ( R f R i n ) V i n and Z i n = R i n V_{out} = -\left(\frac{R_f}{R_{in}}\right) V_{in} \quad \text{and} \quad Z_{in} = R_{in} V o u t = − ( R in R f ) V in and Z in = R in

Non-Inverting Amplifier: Signal enters the non-inverting terminal ( + + + ) directly; R 1 R_1 R 1 and R f R_f R f form a feedback divider to ( − - − ). With Z i n → ∞ Z_{in} \to \infty Z in → ∞ : V o u t = ( 1 + R f R 1 ) V i n V_{out} = \left(1 + \frac{R_f}{R_1}\right) V_{in} V o u t = ( 1 + R 1 R f ) V in

Voltage Follower (Buffer): Direct output-to-inverting feedback ( R f = 0 R_f = 0 R f = 0 ): V o u t = V i n V_{out} = V_{in} V o u t = V in ( A v = 1 A_v = 1 A v = 1 , high Z i n Z_{in} Z in , low Z o u t Z_{out} Z o u t ).

Summing Amplifier: Multiple inputs sum into the inverting virtual ground node without crosstalk: V o u t = − ( R f / R 1 ⋅ V 1 + R f / R 2 ⋅ V 2 ) V_{out} = -(R_f/R_1 \cdot V_1 + R_f/R_2 \cdot V_2) V o u t = − ( R f / R 1 ⋅ V 1 + R f / R 2 ⋅ V 2 ) , used in audio mixers and CTCSS encoders.

Difference Amplifier: Rejects common-mode hum and RF pickup across balanced lines: V o u t = ( R f / R 1 ) ( V 2 − V 1 ) V_{out} = (R_f/R_1)(V_2 - V_1) V o u t = ( R f / R 1 ) ( V 2 − V 1 ) , characterized by its Common-Mode Rejection Ratio (CMRR).

Active Filters: A second-order Sallen-Key low-pass stage rolls off at − 12 dB/octave -12\text{ dB/octave} − 12 dB/octave . Op-amp band-pass filters select SSB speech ( 300 Hz − 2.8 kHz 300\text{ Hz} - 2.8\text{ kHz} 300 Hz − 2.8 kHz ) or narrower CW audio bands without bulky inductors.

Comparator and Schmitt Trigger: Open-loop operation compares inputs, saturating to supply rails ( ± V s a t \pm V_{sat} ± V s a t ). Adding positive feedback introduces hysteresis ( V H = UTP − LTP V_H = \text{UTP} - \text{LTP} V H = UTP − LTP ), eliminating chatter when squaring noisy signals.

Dynamic Limits:

Gain-Bandwidth Product (GBWP): For a dominant-pole voltage-feedback op-amp, f c ≈ GBWP / G N f_c \approx \text{GBWP}/G_N f c ≈ GBWP / G N , where G N G_N G N is noise gain. An inverting stage has G N = 1 + R f / R i n G_N=1+R_f/R_{in} G N = 1 + R f / R in ; a non-inverting stage has noise gain equal to its signal gain.

Slew Rate (SR): Maximum rate of output change ( V / μ s \text{V}/\mu\text{s} V / μ s ), restricting full-power bandwidth to f max = SR / ( 2 π V p ) f_{\text{max}} = \text{SR} / (2 \pi V_p) f max = SR / ( 2 π V p ) .

Circuit Topologies Comparison

Topology Voltage Gain ( A v A_v A v ) Input Impedance ( Z i n Z_{in} Z in ) Output Impedance ( Z o u t Z_{out} Z o u t ) Key Amateur Application

Common Emitter High (inverted) Moderate ( 1 − 5 k Ω 1 - 5\text{ k}\Omega 1 − 5 k Ω ) Moderate-High Audio and IF amplification

Emitter Follower ≈ 1 \approx 1 ≈ 1 (in-phase) High ( 20 − 500 k Ω 20 - 500\text{ k}\Omega 20 − 500 k Ω ) Very Low ( 10 − 50 Ω 10 - 50\ \Omega 10 − 50 Ω ) VFO buffer, impedance matching

Inverting Op-Amp − R f / R i n -R_f / R_{in} − R f / R in R i n R_{in} R in Very Low ( < 1 Ω < 1\ \Omega < 1 Ω ) Audio preamplifiers

Non-Inverting Op-Amp 1 + R f / R 1 1 + R_f / R_1 1 + R f / R 1 High ( > 10 9 Ω > 10^9\ \Omega > 1 0 9 Ω ) Very Low ( < 1 Ω < 1\ \Omega < 1 Ω ) Sensor interfaces

Op-Amp Buffer Unity ( 1 1 1 ) High ( > 10 9 Ω > 10^9\ \Omega > 1 0 9 Ω ) Extremely Low ( < 0.1 Ω < 0.1\ \Omega < 0.1 Ω ) Filter and VFO isolation

Summing Op-Amp − ∑ ( R f / R n ) V n -\sum (R_f/R_n) V_n − ∑ ( R f / R n ) V n R n R_n R n per channel Very Low ( < 1 Ω < 1\ \Omega < 1 Ω ) Audio mixers, CTCSS injection

Difference Op-Amp ( R f / R 1 ) ( V 2 − V 1 ) (R_f/R_1)(V_2 - V_1) ( R f / R 1 ) ( V 2 − V 1 ) R 1 R_1 R 1 Very Low ( < 1 Ω < 1\ \Omega < 1 Ω ) Balanced lines, noise rejection

Worked Engineering Calculations
Example 1: Op-Amp Audio Stage Gain and Bandwidth

Problem: An inverting op-amp stage has R i n = 10 k Ω R_{in} = 10\text{ k}\Omega R in = 10 k Ω and R f = 100 k Ω R_f = 100\text{ k}\Omega R f = 100 k Ω , using an op-amp with GBWP = 3.0 MHz \text{GBWP} = 3.0\text{ MHz} GBWP = 3.0 MHz and SR = 1.5 V / μ s \text{SR} = 1.5\text{ V}/\mu\text{s} SR = 1.5 V / μ s . Calculate the closed-loop gain ( A v A_v A v ), input impedance ( Z i n Z_{in} Z in ), − 3 dB -3\text{ dB} − 3 dB bandwidth ( f c f_c f c ), and maximum peak voltage ( V p V_p V p ) at f = 2.5 kHz f = 2.5\text{ kHz} f = 2.5 kHz without slew distortion.

Solution:

Gain and Input Impedance: A v = − R f R i n = − 100 k Ω 10 k Ω = − 10 ( ∣ A v ∣ = 10 ) and Z i n = R i n = 10 k Ω A_v = -\frac{R_f}{R_{in}} = -\frac{100\text{ k}\Omega}{10\text{ k}\Omega} = -10 \quad (|A_v| = 10) \quad \text{and} \quad Z_{in} = R_{in} = 10\text{ k}\Omega A v = − R in R f = − 10 k Ω 100 k Ω = − 10 ( ∣ A v ∣ = 10 ) and Z in = R in = 10 k Ω

Closed-Loop Bandwidth and Slew Limit: G N = 1 + 100 10 = 11 , f c ≈ GBWP G N = 3 , 000 , 000 Hz 11 ≈ 273 kHz G_N=1+\frac{100}{10}=11, \qquad f_c \approx \frac{\text{GBWP}}{G_N}=\frac{3,000,000\text{ Hz}}{11}\approx273\text{ kHz} G N = 1 + 10 100 = 11 , f c ≈ G N GBWP = 11 3 , 000 , 000 Hz ≈ 273 kHz V p = SR 2 π f = 1.5 × 10 6 V/s 2 × π × 2 , 500 Hz ≈ 95.5 V V_p = \frac{\text{SR}}{2 \pi f} = \frac{1.5 \times 10^6\text{ V/s}}{2 \times \pi \times 2,500\text{ Hz}} \approx 95.5\text{ V} V p = 2 π f SR = 2 × π × 2 , 500 Hz 1.5 × 1 0 6 V/s ≈ 95.5 V

(Output swing is limited by the power rails rather than slew rate).

Example 2: BJT Voltage Divider Bias Operating Point ( Q Q Q -Point)

Problem: An NPN BJT ( β = 100 \beta = 100 β = 100 , V B E = 0.7 V V_{BE} = 0.7\text{ V} V BE = 0.7 V ) is biased with V C C = 12 V V_{CC} = 12\text{ V} V CC = 12 V , R 1 = 33 k Ω R_1 = 33\text{ k}\Omega R 1 = 33 k Ω , R 2 = 10 k Ω R_2 = 10\text{ k}\Omega R 2 = 10 k Ω , R C = 2.2 k Ω R_C = 2.2\text{ k}\Omega R C = 2.2 k Ω , and R E = 680 Ω R_E = 680\ \Omega R E = 680 Ω . Calculate V B V_B V B , I C I_C I C , and V C E V_{CE} V CE .

Solution:

Include Divider Loading: Replace the bias divider by its Thevenin equivalent: V T H = 12 10 33 + 10 = 2.791 V , R T H = 33 × 10 33 + 10 = 7.674 k Ω V_{TH}=12\frac{10}{33+10}=2.791\text{ V}, \qquad R_{TH}=\frac{33\times10}{33+10}=7.674\text{ k}\Omega V T H = 12 33 + 10 10 = 2.791 V , R T H = 33 + 10 33 × 10 = 7.674 k Ω

The base current causes a voltage drop across R T H R_{TH} R T H . With I E = ( β + 1 ) I B I_E=(\beta+1)I_B I E = ( β + 1 ) I B : I B = V T H − V B E R T H + ( β + 1 ) R E = 2.791 − 0.700 7674 + 101 × 680 ≈ 27.38 μ A I_B=\frac{V_{TH}-V_{BE}}{R_{TH}+(\beta+1)R_E}=\frac{2.791-0.700}{7674+101\times680}\approx27.38\ \mu\text{A} I B = R T H + ( β + 1 ) R E V T H − V BE = 7674 + 101 × 680 2.791 − 0.700 ≈ 27.38 μ A I C = β I B ≈ 2.738 mA , V E = ( β + 1 ) I B R E ≈ 1.881 V , V B = V E + 0.700 ≈ 2.581 V I_C=\beta I_B\approx2.738\text{ mA}, \quad V_E=(\beta+1)I_BR_E\approx1.881\text{ V}, \quad V_B=V_E+0.700\approx2.581\text{ V} I C = β I B ≈ 2.738 mA , V E = ( β + 1 ) I B R E ≈ 1.881 V , V B = V E + 0.700 ≈ 2.581 V

Collector-Emitter Voltage: V C = 12 − ( 2.738 mA ) ( 2.2 k Ω ) ≈ 5.976 V V_C=12-(2.738\text{ mA})(2.2\text{ k}\Omega)\approx5.976\text{ V} V C = 12 − ( 2.738 mA ) ( 2.2 k Ω ) ≈ 5.976 V V C E = V C − V E ≈ 5.976 − 1.881 = 4.096 V V_{CE}=V_C-V_E\approx5.976-1.881=4.096\text{ V} V CE = V C − V E ≈ 5.976 − 1.881 = 4.096 V

The collector is above the base, consistent with forward-active NPN operation. Ignoring base current would be an approximation; here it substantially changes the calculated operating point.