Study guide
1.14 Transistor and FET Symbols, Configurations and External Behaviour
ACMA Amateur Radio Standard Recognition Certificate - Theory Exam
Track your progress as you read
Finished sections get a check mark.
1 Chapter 1: Electrical Principles and Components
1.1 Mathematics, Units and Metric Prefixes 1.2 DC Circuits, Voltage, Current, and Ohm's Law 1.3 Power, Energy, and Resistance Calculations 1.4 Resistor Colour Code and Component Symbol Identification 1.5 Capacitors: Construction, Ratings and Safety 1.6 Inductors: Construction, Factors Affecting Inductance and Combinations 1.7 Capacitor and Inductor Combination Calculations 1.8 AC Circuits, Frequency, Wavelength, and RMS Values 1.9 Reactance and Impedance in AC Circuits 1.10 Resonance, Q Factor and Tuned Circuits 1.11 Transformers: Turns Ratio, Impedance Matching and Eddy Currents 1.12 Rectifiers, PIV and Power Supply Smoothing 1.13 Active Components: Semiconductors, Diodes, and Transistors 1.14 Transistor and FET Symbols, Configurations and External Behaviour
2 Chapter 2: Transmitters and Receivers
2.1 Superheterodyne Receiver Architecture and Block Diagrams 2.2 Frequency Converters, IF Amplifiers and Transceiver Sharing 2.3 Receiver Performance: Sensitivity, Selectivity, and AGC 2.4 Signal-to-Noise Ratio and Receiver Noise Performance 2.5 Transmitter Architecture, Oscillators and Frequency Synthesisers 2.6 Transmission Quality: Frequency Drift, Parasitic Oscillation and Over-Modulation 2.7 Modulation Techniques: AM, FM, and SSB 2.8 Amplifier Classes and Power Amplifiers (Class A, B, C, and AB) 2.9 Modulation, Duty Cycle and Rated Transmitter Power 2.10 Transceiver Control: ALC, Squelch, and Digital Modes 2.11 Digital Transmission Modes and Bandwidth
3 Chapter 3: Transmission Lines and Antennas
3.1 Transmission Lines: Coaxial, Twin-Lead, and Characteristic Impedance 3.2 Standing Wave Ratio (SWR) and Reflection Loss 3.3 Impedance Matching, Baluns, and Antenna Tuning Units (ATUs) 3.4 Resonant Antennas: Dipoles, Verticals, and End-Fed Antennas 3.5 Angle of Radiation, Antenna Height and Current Distribution 3.6 Directional Antennas: Yagis, Gain and Radiation Patterns 3.7 Effective Radiated Power: System Gains and Losses
4 Chapter 4: Radio Wave Propagation
4.1 Electromagnetic Waves: Velocity, Wavelength and Polarisation 4.2 Ground Wave, Direct Wave and Line-of-Sight Propagation 4.3 Ionospheric Layers (D, E, F1, F2) and Skywave Propagation 4.4 Critical Frequency, Maximum Usable Frequency (MUF), and Fading 4.5 Solar Activity, Sunspot Cycles, and VHF Anomalous Propagation 4.6 Seasonal and Diurnal Effects on Band Selection
5 Chapter 5: Electrical and RF Measurements
5.1 Multimeter Operation: Voltage, Current, and Resistance Measurements 5.2 RF Power and SWR Measurement (PEP vs. Average Power) 5.3 Frequency Counters, Dummy Loads, and Test Equipment 5.4 Frequency Standards, Crystal Calibrators and Standard-Frequency Transmissions
6 Chapter 6: Interference and Electromagnetic Compatibility (EMC)
6.1 Harmonic Emissions, Spurious Signals, and Transmitter Filtering 6.2 How Interference Enters Television and Broadcast Receivers 6.3 Masthead Amplifier Overload and Audio-Stage Demodulation 6.4 Electromagnetic Interference (EMI), Breakthrough, Ferrites, and EMC 6.5 Filter Types, Response Curves and EMC Filter Selection 6.6 EMC Good Practice: Minimum Power, Balanced Antennas and Feedline Routing 6.7 Vehicle EMC and Resolving Community Interference Complaints
7 Chapter 7: Safety and Environmental Hazards
7.1 Mains Voltage Safety, Earthing, and High-Voltage Capacitors 7.2 Equipment Approval, Mains Wiring and Fuse Practice 7.3 Station Layout, Cabling and Emergency Shut-Off 7.4 Lightning Protection and Station Security 7.5 Electric Shock: Prevention, Rescue and Emergency Response 7.6 Battery, Chemical and Hearing Safety in the Amateur Station 7.7 RF Exposure: EMR Hazards and Safe Distance 7.8 Antenna Erection, Siting and Power Line Safety
1.14 Transistor and FET Symbols, Configurations and External Behaviour
Key Takeaways Explain This Topic AI
The arrow on a bipolar transistor symbol is always on the emitter: it points away from the base for NPN and in towards the base for PNP.
An NPN stage operates with its collector positive with respect to the emitter, while a PNP stage operates with its collector negative.
A silicon transistor needs about 0.6 to 0.7 V between base and emitter before useful collector current flows, and its DC current gain is hFE = IC / IB.
A FET is voltage controlled with a very high input impedance and essentially no gate current, and its gain figure is transconductance rather than current gain.
A common-emitter stage takes its input at the base and its output at the collector and inverts the signal by about 180 degrees, exactly as a common-source stage does with gate and drain.
Last updated: July 2026
1.14 Transistor and FET Symbols, Configurations and External Behaviour
ACMA Exam Focus: Syllabus items 4.30 and 4.31. You must identify the symbols for NPN and PNP bipolar transistors and the field effect transistor, recall their basic external operating characteristics, and identify a device in a common-emitter or common-source configuration. The syllabus is explicit about the depth required: "Candidates are not required to have knowledge of the internal workings of a transistor. Questions about transistor circuits will be simple and limited to common emitter or common source configurations." Learn the symbols, terminal names and external behaviour — not doping and depletion regions.
1. The Bipolar Transistor: Three Terminals
A bipolar junction transistor (BJT) has three terminals:
Emitter — the lead carrying the arrow on the symbol.
Base — the control terminal, drawn as the vertical bar the other leads meet.
Collector — the remaining angled lead, with no arrow.
NPN and PNP symbols are identical apart from that one arrow's direction, so reading the arrow is the whole exercise. The syllabus defines "identify" as picking the right item from a supplied set of diagrams, so these are recognition marks.
- Feature NPN PNP
- Emitter arrow Points away from the base, out of the device Points in towards the base
Collector polarity Collector positive with respect to the emitter Collector negative with respect to the emitter
- Bias to turn the device on Base positive with respect to the emitter Base negative with respect to the emitter
- Emitter usually returns to The negative rail or earth The positive rail
The memory hook is NPN = Not Pointing iN . The arrow is always on the emitter, never the collector, and shows the direction of conventional current.
2. External Behaviour: A Current-Controlled Device
One sentence captures it: a small base current controls a much larger collector current. The ratio is the DC current gain: h F E = I C I B h_{FE} = \frac{I_C}{I_B} h FE = I B I C
and I E = I C + I B I_E = I_C + I_B I E = I C + I B , so the emitter carries the most current.
Nothing happens until the base-emitter junction is forward biased past its turn-on voltage: about 0.6 to 0.7 V for silicon, 0.2 to 0.3 V for germanium (syllabus 4.27). Below that the transistor is an open switch; above it, collector current follows base current.
Worked example. A silicon NPN transistor with h F E = 150 h_{FE} = 150 h FE = 150 has a base current of 40 uA. Find the collector and emitter currents. I C = h F E × I B = 150 × 40 μ A = 6000 μ A = 6 mA I_C = h_{FE} \times I_B = 150 \times 40\ \mu\text{A} = 6000\ \mu\text{A} = 6\ \text{mA} I C = h FE × I B = 150 × 40 μ A = 6000 μ A = 6 mA I E = I C + I B = 6 + 0.04 = 6.04 mA I_E = I_C + I_B = 6 + 0.04 = 6.04\ \text{mA} I E = I C + I B = 6 + 0.04 = 6.04 mA
Note that h F E h_{FE} h FE varies enormously between samples of the same type — about 20 to 800 — and shifts with temperature and current, so practical circuits set the operating point with a bias network and emitter resistor rather than trusting the figure.
3. The Field Effect Transistor
A FET also has three terminals: the source (carriers enter, compare the emitter), the gate (the control terminal, compare the base) and the drain (carriers leave, compare the collector). FETs come in N-channel and P-channel versions and two symbol families:
JFET (junction FET). A continuous channel line with source and drain at either end and the gate entering side-on through an arrowhead. On an N-channel JFET the gate arrow points in towards the channel; on a P-channel JFET it points out .
MOSFET. The channel is drawn as three short broken segments with the gate as a separate bar that does not touch them — a reminder that the gate is insulated from the channel by a thin oxide layer. A substrate arrow alongside points inwards for an N-channel device.
External behaviour to remember:
A FET is voltage controlled : the gate-to-source voltage sets the drain current.
The gate draws essentially no current , so the input impedance is very high — megohms for a JFET, far higher for a MOSFET.
The gain figure is transconductance , g m = Δ I D / Δ V G S g_m = \Delta I_D / \Delta V_{GS} g m = Δ I D /Δ V GS , in siemens (usually millisiemens).
JFETs conduct at zero gate voltage and turn off with reverse gate bias, while enhancement MOSFETs are off until gate voltage is applied.
High input impedance and good strong-signal handling make FETs popular in receiver front ends.
Static precautions for MOSFETs. The gate insulating layer is extraordinarily thin, and static from your body or clothing — at voltages too low to feel — can punch straight through it. The damage is often latent, so the device works then fails days later. Leave it in conductive foam until fitting, wear an earthed anti-static wrist strap, handle it by the body rather than the gate lead, use an earthed-tip soldering iron with the equipment switched off, and never rely on the internal gate-protection diodes.
4. Bipolar versus FET Compared
- Characteristic Bipolar (NPN/PNP) FET (N-channel/P-channel)
- Terminal names Emitter, base, collector Source, gate, drain
- Controlled by Base current Gate voltage
- Control-terminal current Small but real base current Essentially zero gate current
- Input impedance Low to moderate Very high
- Gain parameter Current gain h F E h_{FE} h FE Transconductance g m g_m g m
- Turn-on threshold About 0.6-0.7 V base-emitter (silicon) Set by gate voltage relative to source
- Static-damage risk Low High, especially MOSFETs
- Configuration in the exam Common emitter Common source
- 5. Identifying a Common-Emitter Stage
A stage is named after the terminal common to both input and output circuits — not the terminal the signal is fed into. Find where the input is injected, find where the output is taken, and the remaining terminal names the stage. For a common emitter, look for three features together:
The input is applied to the base , usually through a coupling capacitor.
The output is taken from the collector , where a load resistor runs up to the supply rail.
The emitter is earthed directly, or through a small resistor with a bypass capacitor, so it is common to input and output at signal frequencies.
Its external behaviour: about 180 degrees of phase inversion (drive the base more positive, more collector current flows, more voltage drops across the load resistor, so collector voltage falls), high voltage gain , and a moderate input impedance of a few hundred ohms to a few kilohms. It is the standard general purpose amplifier — audio, IF and driver stages.
6. Identifying a Common-Source Stage
The same drill with FET names: input at the gate , output at the drain across a load resistor or tuned circuit, source earthed or bypassed to earth for signals. Behaviour mirrors the common emitter — about 180 degrees of phase inversion and high voltage gain — but with a very high input impedance that barely loads the preceding stage.
Worked example. A common-source stage runs from a 15 V supply with a drain load resistor R D = 1.2 R_D = 1.2 R D = 1.2 kilohms and drain current I D = 8 I_D = 8 I D = 8 mA. Find the voltage across the load and the drain voltage. V R D = I D × R D = 0.008 × 1200 = 9.6 V V_{R_D} = I_D \times R_D = 0.008 \times 1200 = 9.6\ \text{V} V R D = I D × R D = 0.008 × 1200 = 9.6 V V D = 15 − 9.6 = 5.4 V V_D = 15 - 9.6 = 5.4\ \text{V} V D = 15 − 9.6 = 5.4 V
The drain idles at about 5.4 V, leaving headroom for the output to swing both ways without hitting the supply rail or cut-off.
7. Other Configurations, for Contrast
The paper limits transistor questions to common-emitter and common-source stages, but recognising the alternatives helps eliminate wrong answers.
- Configuration Input Output Phase Notable for
- Common emitter / common source Base / gate Collector / drain Inverted High voltage and power gain; exam stages
Common collector / common drain (follower) Base / gate Emitter / source Not inverted Gain just under 1; buffer stage
Common base / common gate Emitter / source Collector / drain Not inverted Low input impedance; VHF and UHF front ends
Elimination rule: if the output is taken from the emitter, it is not a common-emitter stage, however the transistor is drawn.
8. Quick Recap
The arrow sits on the emitter: out for NPN, in for PNP.
NPN runs with the collector positive with respect to the emitter; PNP negative.
Silicon needs roughly 0.6-0.7 V base-emitter to conduct, and h F E = I C / I B h_{FE} = I_C / I_B h FE = I C / I B .
A FET is voltage controlled, draws no significant gate current and has a very high input impedance.
Common emitter: base in, collector out, emitter common, inverted. Common source: gate in, drain out, source common, inverted.