5.2 Combinational & Sequential Logic

FE Electrical and Computer Exam Exam

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1 FE Electrical & Computer: Exam Map, Handbook & Strategy

1.1 Current Exam Facts 1.2 CBT Format & Scaled Scoring 1.3 The FE Reference Handbook 1.4 Approved Calculators & Test-Day Logistics 1.5 Study Plan & Time Strategy

2 Mathematics, Economics & Ethics

2.1 Algebra, Calculus & Differential Equations 2.2 Complex Numbers & Laplace Transforms 2.3 Probability & Statistics 2.4 Engineering Economics 2.5 Ethics & Professional Practice

3 Circuits, Electronics & Electromagnetics

3.1 DC Circuit Analysis 3.2 AC Steady-State & Phasors 3.3 Transient Response (RL, RC, RLC) 3.4 Electronics & Devices 3.5 Electromagnetics

4 Signals, Systems, Controls & Communications

4.1 Linear Systems & Transfer Functions 4.2 Signal Processing & Sampling 4.3 Control Systems 4.4 Communications

5 Digital Systems, Computers, Networks & Software

5.1 Number Systems & Boolean Algebra 5.2 Combinational & Sequential Logic 5.3 Computer Architecture & Microprocessors 5.4 Computer Networks 5.5 Software Engineering & Algorithms

6 Power, Materials & Final Readiness

6.1 Power Fundamentals & Three-Phase 6.2 Transformers & Rotating Machines 6.3 Power Electronics & Transmission 6.4 Properties of Electrical Materials & Engineering Sciences 6.5 Integrated Practice & Final Readiness

5.2 Combinational & Sequential Logic

Key Takeaways Explain This Topic AI

Combinational output depends only on present inputs; sequential output depends on inputs plus stored state and is clocked.

A multiplexer selects one of n inputs using log2(n) select lines; an n-to-2^n decoder activates exactly one output line.

A D flip-flop captures D on the clock edge; a JK toggles when J=K=1; a T flip-flop toggles each edge when T=1.

An n-flip-flop binary counter cycles through 2^n states, so a mod-10 counter needs 4 flip-flops plus reset-at-10 logic.

A Moore machine's outputs depend only on the current state; a Mealy machine's outputs depend on state and present inputs.

Last updated: June 2026

Combinational vs sequential logic

The FE separates digital circuits into two families. Combinational logic produces an output that depends only on the present input combination, with no memory; AND/OR networks, multiplexers, decoders, and adders are combinational and are analyzed with a truth table . Sequential logic adds memory elements, so the output depends on both present inputs and stored state , and it is synchronized by a clock ; it is analyzed with a state/transition table .

Recognizing the family tells you the right tool: write a truth table for combinational problems, and a state diagram or excitation table for sequential ones. Gates are the atoms of both.

Basic gate truth table

Know these by heart; the FE rarely gives you time to derive them.

• A B AND OR NAND NOR XOR
• 0 0 0 0 1 1 0
• 0 1 0 1 1 0 1
• 1 0 0 1 1 0 1
• 1 1 1 1 0 0 0

XOR is 1 only when the inputs differ, which makes it the core of adders and parity circuits. NAND is 0 only when all inputs are 1; with NOR it is universal, so any logic function can be built from NAND gates alone. XNOR (not shown) is the complement of XOR and equals 1 when inputs match - an equality detector.

Combinational building blocks

FE questions reuse a small set of standard combinational modules:

Multiplexer (MUX): routes one of n data inputs to a single output, chosen by log2(n) select lines. A 4-to-1 MUX needs 2 select lines; an 8-to-1 needs 3. A MUX can implement any Boolean function directly - a favorite exam shortcut.

Demultiplexer: the reverse, steering one input to one of several outputs.

Decoder: turns an n-bit code into one active line out of 2^n; a 3-to-8 decoder activates exactly one of eight outputs.

Encoder: the reverse of a decoder, producing an n-bit code from an active input.

Half adder: sums two bits, S = A XOR B, carry = A AND B.

Full adder: sums two bits plus carry-in; chaining n full adders builds a ripple-carry adder , whose worst-case delay grows with n as the carry propagates.

Worked combinational example: a 4-to-1 MUX has data inputs D0-D3 and select lines S1,S0. When S1S0 = 10 (binary 2), the output equals D2; the Boolean form is Y = S1'S0'D0 + S1'S0 D1 + S1 S0' D2 + S1 S0 D3. To implement a 3-input function on a 4-to-1 MUX, drive the two select lines with two of the variables and wire each data input to 0, 1, the third variable, or its complement as the truth table requires.

Latches and flip-flops: the storage element

A latch is level-sensitive (transparent while the enable is high); a flip-flop is edge-triggered (samples only at the clock edge). The FE usually means edge-triggered when it says 'flip-flop.' Expect the behavior of four cells:

SR latch: S=1 sets Q=1, R=1 resets Q=0; S=R=1 is forbidden (indeterminate).

D flip-flop: Q takes the value of D at the active clock edge - the simple default storage cell.

JK flip-flop: J=K=0 holds, J=1/K=0 sets, J=0/K=1 resets, J=K=1 toggles Q.

T flip-flop: toggles Q each edge when T=1 - the natural counter element (a JK with J=K tied together).

Setup time and hold time define the window around the clock edge during which D must stay stable; violating them causes metastability .