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12.1 Foundational ICT Terminology, Acronyms & Computer Architecture
Chhattisgarh State Eligibility Test CG SET
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1 Chapter 1: Exam Structure, Blueprint & Preparation Strategy
1.1 Exam Blueprint, Marking Scheme & Qualifying Cutoffs 1.2 Eligibility Requirements, Master's Degree Criteria & Domicile Policy 1.3 Paper I Strategic Study Plan, Time Allocation & OMR Tactics
2 Chapter 2: Teaching Aptitude — Concepts, Objectives & Learner Characteristics
2.1 Concepts, Objectives & Levels of Teaching 2.2 Learner Characteristics & Individual Differences 2.3 Factors Influencing Teaching Effectiveness & Instructional Facilities
3 Chapter 3: Teaching Aptitude — Methods, Support Systems & Evaluation
3.1 Teacher-Centered vs. Learner-Centered Methods & Modern Pedagogy 3.2 Teaching Support Systems & Online Digital Platforms (SWAYAM, MOOCs) 3.3 Evaluation Systems, CBCS & Assessment Innovations
4 Chapter 4: Research Aptitude — Paradigms, Types & Methodologies
4.1 Meaning, Objectives, Characteristics & Types of Research 4.2 Epistemological Approaches: Positivism vs. Post-Positivist Philosophies 4.3 Core Research Methods: Descriptive, Experimental & Historical
5 Chapter 5: Research Aptitude — Process, Ethics & Scholarly Writing
5.1 Systematic Steps of Research & Hypothesis Testing 5.2 Thesis, Dissertation & Scholarly Article Writing 5.3 Application of ICT in Research & Research Ethics
6 Chapter 6: Reading Comprehension — Critical Analysis & Interpretation
6.1 Critical Reading Strategies: Structure, Main Ideas & Skimming vs. Scanning 6.2 Inferential Analysis, Contextual Vocabulary & Author's Tone 6.3 Question-Solving Tactics & Eliminating Distractors in Academic Passages
7 Chapter 7: Communication in Education & Mass Media
7.1 Meaning, Types & Characteristics of Communication 7.2 Effective Classroom Communication: Verbal/Non-Verbal Dynamics & Immediacy 7.3 Communication Barriers & The Role of Mass Media in Society
8 Chapter 8: Mathematical Reasoning & Quantitative Aptitude
8.1 Number Series, Letter Series, Coding-Decoding & Relationships 8.2 Fractions, Ratios, Proportions & Percentage Mastery 8.3 Profit & Loss, Interest, Discounting, Speed-Distance & Averages
9 Chapter 9: Logical Reasoning — Western Deductive & Inductive Logic
9.1 Structure of Arguments & Categorical Propositions 9.2 Formal & Informal Fallacies & Connotation vs. Denotation 9.3 Classical Square of Opposition & Venn Diagrams for Validity
10 Chapter 10: Logical Reasoning — Indian Logic & Nyaya Epistemology
10.1 Indian Logic: Six Pramanas (Means of Valid Knowledge) 10.2 Structure and Types of Anumana (Inference), Vyapti & Hetu 10.3 Hetvabhasa: Fallacies of Inference in Nyaya Logic
11 Chapter 11: Data Interpretation & Quantitative Representation
11.1 Sources, Acquisition & Classification of Quantitative and Qualitative Data 11.2 Graphical Representation: Bar Charts, Histograms, Pie Charts & Line Graphs 11.3 Table Charts, Cross-Tabulation & Data Interpretation for Governance 11.4 Mapping of Data & Data in Governance
12 Chapter 12: Information & Communication Technology (ICT)
12.1 Foundational ICT Terminology, Acronyms & Computer Architecture 12.2 Internet Architecture, Intranets, Email & Video Conferencing Mechanics 12.3 National Digital Initiatives in Higher Education & ICT Governance
13 Chapter 13: People, Development & Environment — Goals & Pollution
13.1 Development and Environment: Millennium & Sustainable Development Goals 13.2 Anthropogenic Impacts & Environmental Pollution Types 13.3 Health Impacts of Pollutants, Heavy Metals & Climate Dynamics
14 Chapter 14: People, Development & Environment — Energy, Hazards & Treaties
14.1 Renewable & Non-Renewable Energy Resources and India's Energy Transition 14.2 Natural Hazards, Disasters & Disaster Management Architecture 14.3 Environmental Legislation, NAPCC & International Conventions
15 Chapter 15: Higher Education System — Historical Evolution & Modalities
15.1 Higher Learning & Education in Ancient India 15.2 Evolution of Higher Learning in Post-Independence India & NEP 2020 15.3 Oriental, Conventional, Non-Conventional & Vocational Education
16 Chapter 16: Higher Education System — Governance, Ethics & Policy
16.1 Value Education & Environmental Education in Academic Curricula 16.2 Regulatory Landscape: UGC, Professional Councils, NAAC & NIRF 16.3 Higher Education Governance & Administration in Chhattisgarh State
12.1 Foundational ICT Terminology, Acronyms & Computer Architecture
Key Takeaways Explain This Topic AI
Data storage metrics ascend exponentially from binary digits (bits) and 4-bit nibbles to 8-bit bytes and binary multiplier tiers ( 2 10 2^{10} 2 10 or 1,024 bytes: KB, MB, GB, TB, PB, EB, ZB, YB), establishing a crucial distinction between binary IEC memory capacity ( 2 10 2^{10} 2 10 ) and decimal SI storage marketing ( 10 3 10^3 1 0 3 ).
Number system conversions rely on positional radix mathematics across Binary (base-2), Octal (base-8), Decimal (base-10), and Hexadecimal (base-16), using successive division/multiplication algorithms and direct bit-grouping (3 bits for octal, 4 bits for hex).
Character encoding standards evolved from standard 7-bit ASCII (128 code points) and extended 8-bit ASCII / ISCII (256 code points) to universal Unicode (UTF-8, UTF-16, UTF-32), enabling comprehensive cross-platform multilingual digital representation.
The Von Neumann architecture defines modern stored-program computing, integrating the Central Processing Unit (ALU, CU, Registers), system buses (data, address, control), and a hierarchical memory model to balance processing speed, cost, and capacity.
System storage contrasts volatile, ultra-fast primary memory (SRAM flip-flop cache and DRAM capacitor-transistor main memory requiring dynamic electrical refresh) with non-volatile firmware and secondary storage (Mask ROM, PROM, UV-erasable EPROM, EEPROM, and block-erased NAND Flash).
Last updated: October 2026
Foundational ICT Terminology, Acronyms & Computer Architecture
Core Principle: In computer systems and digital informatics, information is represented, processed, and stored through physical voltage states mapped to binary mathematics. Mastery of data representation scales, positional number conversion algorithms, CPU microarchitecture, and memory volatility is essential for navigating modern academic technology and standardized aptitude assessments.
1. Data Representation and the Memory Unit Hierarchy
All digital computational systems operate on binary state logic (presence or absence of electrical voltage, magnetic charge orientation, or optical pit reflection). The fundamental physical atom of digital information is the bit ( bi nary digi t ), which can assume only one of two mutually exclusive discrete states: 0 0 0 (low voltage / off) or 1 1 1 (high voltage / on).
The Fundamental Units: Bit, Nibble, and Byte
Bit (b): The smallest elementary unit of digital storage. A single bit can encode exactly 2 1 = 2 2^1 = 2 2 1 = 2 unique distinct states ( 0 0 0 or 1 1 1 ).
Nibble (Half-Byte): A sequence of 4 consecutive bits . A nibble can represent 2 4 = 16 2^4 = 16 2 4 = 16 unique binary combinations ( 0000 2 0000_2 000 0 2 to 1111 2 1111_2 111 1 2 ). Because 16 values correspond exactly to the base of the hexadecimal number system, one nibble represents precisely one hexadecimal digit (0–9, A–F).
Byte (B): A contiguous sequence of 8 bits . A byte represents 2 8 = 256 2^8 = 256 2 8 = 256 distinct combinations ( 00000000 2 00000000_2 0000000 0 2 to 11111111 2 11111111_2 1111111 1 2 ), spanning decimal values from 0 through 255. In computer architecture, the byte is the fundamental addressable unit of memory and the standard building block for alphanumeric characters in legacy encoding sets.
Word: The natural data unit processed concurrently by a specific CPU architecture in a single clock cycle. Common architectures feature 32-bit (4 bytes) or 64-bit (8 bytes) word lengths. A larger word size allows the CPU to process more data per cycle and directly address exponentially larger physical memory spaces.
The Decimal ( 10 3 10^3 1 0 3 ) vs. Binary ( 2 10 2^{10} 2 10 ) Memory Convention
A frequent source of confusion—and a perennial exam question topic—stems from the divergence between decimal metric prefixes (standardized by the International System of Units, SI) and binary memory prefixes (standardized by the International Electrotechnical Commission, IEC):
Decimal Metric Scale (Powers of 10): Telecommunications engineers, data transmission networks, and secondary storage drive manufacturers define units in powers of 10: 1 Kilobyte (KB) = 10 3 Bytes = 1,000 Bytes \text{1 Kilobyte (KB)} = 10^3 \text{ Bytes} = 1{,}000 \text{ Bytes} 1 Kilobyte (KB) = 1 0 3 Bytes = 1 , 000 Bytes 1 Megabyte (MB) = 10 6 Bytes = 1,000,000 Bytes \text{1 Megabyte (MB)} = 10^6 \text{ Bytes} = 1{,}000{,}000 \text{ Bytes} 1 Megabyte (MB) = 1 0 6 Bytes = 1 , 000 , 000 Bytes 1 Gigabyte (GB) = 10 9 Bytes = 1,000,000,000 Bytes \text{1 Gigabyte (GB)} = 10^9 \text{ Bytes} = 1{,}000{,}000{,}000 \text{ Bytes} 1 Gigabyte (GB) = 1 0 9 Bytes = 1 , 000 , 000 , 000 Bytes 1 Terabyte (TB) = 10 12 Bytes = 1,000,000,000,000 Bytes \text{1 Terabyte (TB)} = 10^{12} \text{ Bytes} = 1{,}000{,}000{,}000{,}000 \text{ Bytes} 1 Terabyte (TB) = 1 0 12 Bytes = 1 , 000 , 000 , 000 , 000 Bytes
Binary Scale (Powers of 2): In computer architecture, because address buses use binary logic, memory capacity scales in powers of 2. The binary multiple closest to 1,000 is 2 10 = 1,024 2^{10} = 1{,}024 2 10 = 1 , 024 . The IEC formalized these as Kibibyte (KiB) , Mebibyte (MiB) , and Gibibyte (GiB) , though general computer operating systems still frequently label binary units using traditional KB/MB/GB abbreviations: 1 Kibibyte (KiB / traditional KB) = 2 10 Bytes = 1,024 Bytes \text{1 Kibibyte (KiB / traditional KB)} = 2^{10} \text{ Bytes} = 1{,}024 \text{ Bytes} 1 Kibibyte (KiB / traditional KB) = 2 10 Bytes = 1 , 024 Bytes 1 Mebibyte (MiB / traditional MB) = 2 20 Bytes = 1,024 × 1,024 = 1,048,576 Bytes \text{1 Mebibyte (MiB / traditional MB)} = 2^{20} \text{ Bytes} = 1{,}024 \times 1{,}024 = 1{,}048{,}576 \text{ Bytes} 1 Mebibyte (MiB / traditional MB) = 2 20 Bytes = 1 , 024 × 1 , 024 = 1 , 048 , 576 Bytes 1 Gibibyte (GiB / traditional GB) = 2 30 Bytes = 1,024 3 = 1,073,741,824 Bytes \text{1 Gibibyte (GiB / traditional GB)} = 2^{30} \text{ Bytes} = 1{,}024^3 = 1{,}073{,}741{,}824 \text{ Bytes} 1 Gibibyte (GiB / traditional GB) = 2 30 Bytes = 1 , 02 4 3 = 1 , 073 , 741 , 824 Bytes 1 Tebibyte (TiB / traditional TB) = 2 40 Bytes = 1,024 4 = 1,099,511,627,776 Bytes \text{1 Tebibyte (TiB / traditional TB)} = 2^{40} \text{ Bytes} = 1{,}024^4 = 1{,}099{,}511{,}627{,}776 \text{ Bytes} 1 Tebibyte (TiB / traditional TB) = 2 40 Bytes = 1 , 02 4 4 = 1 , 099 , 511 , 627 , 776 Bytes
Exam Trap Alert: Why does a brand-new 1 Terabyte (1,000,000,000,000 Bytes) solid-state drive or hard drive show only approximately 931.32 Gigabytes when installed in Microsoft Windows? Storage manufacturers sell drive capacities based on decimal metric definitions ( 10 12 10^{12} 1 0 12 bytes), but operating system software computes storage capacity in binary Gibibytes ( 10 12 ÷ 1,024 3 ≈ 931.32 GiB 10^{12} \div 1{,}024^3 \approx 931.32\text{ GiB} 1 0 12 ÷ 1 , 02 4 3 ≈ 931.32 GiB ). No storage is missing; it is purely a mathematical artifact of the decimal-versus-binary conversion discrepancy.
Comprehensive Hierarchy of Data Storage Units
Competitive examinations regularly test the precise ascending order of large-scale digital storage capacities. Candidates should know the standard hierarchy from Bit to Quettabyte:
- Unit Name Standard Symbol Binary Exponential Value Decimal Metric Value Relative Equivalence
- Bit b 2 0 2^0 2 0 bits 1 1 1 bit Single binary digit ( 0 0 0 or 1 1 1 )
- Nibble — 4 4 4 bits 4 4 4 bits Half a byte / 1 hexadecimal character
- Byte B 2 3 2^3 2 3 bits 8 8 8 bits 1 alphanumeric character (ASCII)
- Kilobyte KB / KiB 2 10 2^{10} 2 10 Bytes 10 3 10^3 1 0 3 Bytes 1,024 1{,}024 1 , 024 Bytes
- Megabyte MB / MiB 2 20 2^{20} 2 20 Bytes 10 6 10^6 1 0 6 Bytes 1,024 1{,}024 1 , 024 Kilobytes
- Gigabyte GB / GiB 2 30 2^{30} 2 30 Bytes 10 9 10^9 1 0 9 Bytes 1,024 1{,}024 1 , 024 Megabytes
- Terabyte TB / TiB 2 40 2^{40} 2 40 Bytes 10 12 10^{12} 1 0 12 Bytes 1,024 1{,}024 1 , 024 Gigabytes
- Petabyte PB / PiB 2 50 2^{50} 2 50 Bytes 10 15 10^{15} 1 0 15 Bytes 1,024 1{,}024 1 , 024 Terabytes
- Exabyte EB / EiB 2 60 2^{60} 2 60 Bytes 10 18 10^{18} 1 0 18 Bytes 1,024 1{,}024 1 , 024 Petabytes
- Zettabyte ZB / ZiB 2 70 2^{70} 2 70 Bytes 10 21 10^{21} 1 0 21 Bytes 1,024 1{,}024 1 , 024 Exabytes
- Yottabyte YB / YiB 2 80 2^{80} 2 80 Bytes 10 24 10^{24} 1 0 24 Bytes 1,024 1{,}024 1 , 024 Zettabytes
- Ronnabyte RB — 10 27 10^{27} 1 0 27 Bytes 1,000 1{,}000 1 , 000 Yottabytes
- Quettabyte QB — 10 30 10^{30} 1 0 30 Bytes 1,000 1{,}000 1 , 000 Ronnabytes
Note: In November 2022 the 27th General Conference on Weights and Measures (CGPM) adopted the SI prefixes ronna ( 10 27 10^{27} 1 0 27 ) and quetta ( 10 30 10^{30} 1 0 30 ), so the units after the yottabyte are the ronnabyte (RB) and quettabyte (QB). Older quiz books list "brontobyte" and "geopbyte", which were never adopted as standards.
2. Radix Number Systems and Conversion Algorithms
A radix (base) defines the total number of unique digits or symbols utilized by a positional numeral system. The value of any digit depends on both the symbol itself and its weighted position relative to the radix point.
The Four Standard Computing Number Systems
Binary System (Base-2): Uses digits { 0 , 1 } \{0, 1\} { 0 , 1 } . Fundamental language of physical transistor circuitry.
Octal System (Base-8): Uses digits { 0 , 1 , 2 , 3 , 4 , 5 , 6 , 7 } \{0, 1, 2, 3, 4, 5, 6, 7\} { 0 , 1 , 2 , 3 , 4 , 5 , 6 , 7 } . Historically used in computing because each octal digit corresponds exactly to 3 binary bits ( 2 3 = 8 2^3 = 8 2 3 = 8 ).
Decimal System (Base-10): Uses digits { 0 , 1 , 2 , 3 , 4 , 5 , 6 , 7 , 8 , 9 } \{0, 1, 2, 3, 4, 5, 6, 7, 8, 9\} { 0 , 1 , 2 , 3 , 4 , 5 , 6 , 7 , 8 , 9 } . Standard human arithmetic system.
Hexadecimal System (Base-16): Uses 16 alphanumeric symbols: { 0 , 1 , 2 , 3 , 4 , 5 , 6 , 7 , 8 , 9 , A, B, C, D, E, F } \{0, 1, 2, 3, 4, 5, 6, 7, 8, 9, \text{A, B, C, D, E, F}\} { 0 , 1 , 2 , 3 , 4 , 5 , 6 , 7 , 8 , 9 , A, B, C, D, E, F } . The alphabetic characters represent numerical values from 10 to 15: A = 10 , B = 11 , C = 12 , D = 13 , E = 14 , F = 15 \text{A} = 10, \quad \text{B} = 11, \quad \text{C} = 12, \quad \text{D} = 13, \quad \text{E} = 14, \quad \text{F} = 15 A = 10 , B = 11 , C = 12 , D = 13 , E = 14 , F = 15 Because 2 4 = 16 2^4 = 16 2 4 = 16 , each hexadecimal digit corresponds exactly to a 4-bit nibble , providing a compact, human-readable shorthand for binary byte streams, memory addresses, and IPv6 configurations.
- Step-by-Step Conversion Algorithms with Worked Numerical Examples
- Case 1: Decimal to Binary (Successive Division by 2)
To convert an integer from decimal (base-10) to binary (base-2), divide the integer successively by 2, recording each integer quotient and remainder until the quotient reaches 0. The binary equivalent is formed by reading the remainders from bottom to top (Most Significant Bit [MSB] to Least Significant Bit [LSB]).
Worked Example: Convert ( 45 ) 10 (45)_{10} ( 45 ) 10 to Binary.
- 45 ÷ 2 = 22 45 \div 2 = 22 45 ÷ 2 = 22 , remainder 1 (LSB)
- 22 ÷ 2 = 11 22 \div 2 = 11 22 ÷ 2 = 11 , remainder 0
- 11 ÷ 2 = 5 11 \div 2 = 5 11 ÷ 2 = 5 , remainder 1
- 5 ÷ 2 = 2 5 \div 2 = 2 5 ÷ 2 = 2 , remainder 1
- 2 ÷ 2 = 1 2 \div 2 = 1 2 ÷ 2 = 1 , remainder 0
- 1 ÷ 2 = 0 1 \div 2 = 0 1 ÷ 2 = 0 , remainder 1 (MSB)
Reading remainders from bottom (MSB) to top (LSB): ( 45 ) 10 = ( 101101 ) 2 (45)_{10} = (101101)_2 ( 45 ) 10 = ( 101101 ) 2 .
Case 2: Binary to Decimal (Positional Weighting)
To convert binary to decimal, multiply each binary digit d i d_i d i by its positional power of 2 ( 2 i 2^i 2 i , starting with i = 0 i=0 i = 0 for the rightmost bit), then sum all products: Value = ∑ i = 0 n − 1 d i × 2 i \text{Value} = \sum_{i=0}^{n-1} d_i \times 2^i Value = ∑ i = 0 n − 1 d i × 2 i
Worked Example: Convert ( 110101 ) 2 (110101)_2 ( 110101 ) 2 to Decimal. Value = ( 1 × 2 5 ) + ( 1 × 2 4 ) + ( 0 × 2 3 ) + ( 1 × 2 2 ) + ( 0 × 2 1 ) + ( 1 × 2 0 ) \text{Value} = (1 \times 2^5) + (1 \times 2^4) + (0 \times 2^3) + (1 \times 2^2) + (0 \times 2^1) + (1 \times 2^0) Value = ( 1 × 2 5 ) + ( 1 × 2 4 ) + ( 0 × 2 3 ) + ( 1 × 2 2 ) + ( 0 × 2 1 ) + ( 1 × 2 0 ) Value = 32 + 16 + 0 + 4 + 0 + 1 = ( 53 ) 10 \text{Value} = 32 + 16 + 0 + 4 + 0 + 1 = (53)_{10} Value = 32 + 16 + 0 + 4 + 0 + 1 = ( 53 ) 10 .
Case 3: Fractional Conversions (Successive Multiplication by 2)
For fractional decimal numbers, multiply the fraction successively by 2. The integer part of the product becomes the binary digit, and the fractional remainder is multiplied again, proceeding left-to-right.
Worked Example: Convert ( 0.625 ) 10 (0.625)_{10} ( 0.625 ) 10 to Binary.
- 0.625 × 2 = 1.25 ⟹ 0.625 \times 2 = \mathbf{1}.25 \implies 0.625 × 2 = 1 .25 ⟹ integer digit 1 (MSB)
- 0.25 × 2 = 0.50 ⟹ 0.25 \times 2 = \mathbf{0}.50 \implies 0.25 × 2 = 0 .50 ⟹ integer digit 0
- 0.50 × 2 = 1.00 ⟹ 0.50 \times 2 = \mathbf{1}.00 \implies 0.50 × 2 = 1 .00 ⟹ integer digit 1 (terminates)
Reading integers from top to bottom: ( 0.625 ) 10 = ( 0.101 ) 2 (0.625)_{10} = (0.101)_2 ( 0.625 ) 10 = ( 0.101 ) 2 .
Combining whole and fractional parts: ( 45.625 ) 10 = ( 101101.101 ) 2 (45.625)_{10} = (101101.101)_2 ( 45.625 ) 10 = ( 101101.101 ) 2 .
Case 4: Binary to Hexadecimal (Direct 4-Bit Grouping)
Because 16 = 2 4 16 = 2^4 16 = 2 4 , conversion between binary and hexadecimal requires no division. Group the binary string into clusters of 4 bits starting from the radix point (moving left for integers, padding leading zeros if necessary; moving right for fractions, padding trailing zeros). Replace each 4-bit nibble with its hexadecimal symbol.
Worked Example: Convert ( 111010110010 ) 2 (111010110010)_2 ( 111010110010 ) 2 to Hexadecimal.
- Partition into 4-bit nibbles: 1110 | 1011 | 0010
- Convert 1110 to decimal: 8 + 4 + 2 + 0 = 14 ⟹ E 8 + 4 + 2 + 0 = 14 \implies \mathbf{E} 8 + 4 + 2 + 0 = 14 ⟹ E
- Convert 1011 to decimal: 8 + 0 + 2 + 1 = 11 ⟹ B 8 + 0 + 2 + 1 = 11 \implies \mathbf{B} 8 + 0 + 2 + 1 = 11 ⟹ B
Convert 0010 to decimal: 0 + 0 + 2 + 0 = 2 ⟹ 2 0 + 0 + 2 + 0 = 2 \implies \mathbf{2} 0 + 0 + 2 + 0 = 2 ⟹ 2 Result: ( 111010110010 ) 2 = ( EB 2 ) 16 (111010110010)_2 = (\text{EB}2)_{16} ( 111010110010 ) 2 = ( EB 2 ) 16 .
Case 5: Decimal to Hexadecimal (Successive Division by 16)
Divide the decimal number successively by 16, noting remainders, and map remainders ≥ 10 \ge 10 ≥ 10 to letters A–F.
Worked Example: Convert ( 754 ) 10 (754)_{10} ( 754 ) 10 to Hexadecimal.
- 754 ÷ 16 = 47 754 \div 16 = 47 754 ÷ 16 = 47 , remainder 2 (LSB)
- 47 ÷ 16 = 2 47 \div 16 = 2 47 ÷ 16 = 2 , remainder 15 ⟹ F 15 \implies \mathbf{F} 15 ⟹ F
- 2 ÷ 16 = 0 2 \div 16 = 0 2 ÷ 16 = 0 , remainder 2 (MSB)
Reading from bottom to top: ( 754 ) 10 = ( 2 F 2 ) 16 (754)_{10} = (2\text{F}2)_{16} ( 754 ) 10 = ( 2 F 2 ) 16 .
Character Encoding Schemes
Computers encode text by mapping characters to numeric binary bit patterns.
ASCII (American Standard Code for Information Interchange):
Standard 7-bit ASCII: First published in 1963 by the American Standards Association (ASA, now ANSI). Encodes 2 7 = 128 2^7 = 128 2 7 = 128 distinct characters (codes 0 to 127), including 33 non-printable control characters (such as Null, Carriage Return, Line Feed) and 95 printable characters (English alphabet A–Z, a–z, digits 0–9, punctuation).
Key Decimal Anchor Values (Frequently Tested):
- Character '0' to '9' ⟹ \implies ⟹ Decimal 48 to 57 (Binary 00110000 to 00111001 )
- Uppercase 'A' to 'Z' ⟹ \implies ⟹ Decimal 65 to 90 ( 'A' = 65, 'B' = 66, ..., 'Z' = 90)
- Lowercase 'a' to 'z' ⟹ \implies ⟹ Decimal 97 to 122 ( 'a' = 97, 'b' = 98, ..., 'z' = 122)
Diagnostic Observation: The numerical difference between any uppercase letter and its lowercase counterpart is exactly 32 ( 97 − 65 = 32 97 - 65 = 32 97 − 65 = 32 ). In binary, toggling the 6th bit (weight 32, bit index 5) converts between uppercase and lowercase.
Extended 8-bit ASCII: Utilizes all 8 bits of a byte ( 2 8 = 256 2^8 = 256 2 8 = 256 characters, codes 0 to 255). Retains standard ASCII for codes 0–127 and adds codes 128–255 for accented Latin characters, mathematical symbols, and graphical box-drawing borders.
ISCII (Indian Script Code for Information Interchange):
Developed in 1988 under the Department of Electronics and adopted by the Bureau of Indian Standards (BIS) as IS 13194:1991, an 8-bit character encoding specifically designed to encode Indian regional scripts (Devanagari, Bengali, Gurmukhi, Gujarati, Oriya, Tamil, Telugu, Kannada, Malayalam, and Assamese).
Retains standard 7-bit ASCII in the lower half (codes 0–127) for English compatibility, while allocating the upper 128 codes (128–255) for Indian phonetic alphabets. Because all major Indian scripts share a common Brahmi origin, ISCII maps equivalent phonemes across different regional scripts to the same code point.
Unicode (Universal Coded Character Set):
A modern international computing standard maintained by the Unicode Consortium designed to encode every written character in human linguistic history, as well as emojis and mathematical symbols, with a repertoire that grows with each new version (now more than 150,000 characters across over 160 modern and historic scripts).
UTF-8 (Unicode Transformation Format, 8-bit): Variable-length encoding using 1 to 4 bytes per character. Crucially, UTF-8 is 100% backward-compatible with 7-bit ASCII ; all ASCII characters are represented as single bytes with identical values (0–127). It powers over 98% of the World Wide Web.
UTF-16: Variable-length encoding using 2 or 4 bytes per code point. Widely adopted as the internal memory encoding for modern operating system runtimes (Microsoft Windows, Java Virtual Machine, JavaScript engines).
UTF-32: Fixed-length encoding using exactly 4 bytes (32 bits) per character. Fast random indexing in memory, but quadruples storage requirements for standard Latin text.
3. Computer Hardware Architecture: The Von Neumann Model
In 1945, mathematician and physicist John von Neumann published First Draft of a Report on the EDVAC , formulating the theoretical architecture that underpins virtually all contemporary general-purpose computers. VON NEUMANN ARCHITECTURE
- ┌────────────────────────────────────────────────────────┐
- │ CENTRAL PROCESSING UNIT (CPU) │
- │ ┌───────────────────────┐ ┌──────────────────────┐ │
- │ │ Control Unit (CU) │ │ Registers (PC, MAR, │ │
- │ │ - Instruction Decoder │ │ MDR, IR, AC, etc.) │ │
- │ └───────────┬───────────┘ └──────────┬───────────┘ │
- │ │ │ │
- │ ┌───────────┴──────────────────────────┴───────────┐ │
- │ │ Arithmetic Logic Unit (ALU) │ │
- │ └──────────────────────────────────────────────────┘ │
- └──────────────────────────┬─────────────────────────────┘
- │ (System Bus: Control, Address, Data)
- ┌──────────────────────────┴─────────────────────────────┐
- │ SHARED PRIMARY MEMORY (RAM / ROM) │
- │ [Stored Instructions] & [Data Operands] │
- └──────────────────────────┬─────────────────────────────┘
- │
- ┌──────────────────────────┴─────────────────────────────┐
- │ INPUT / OUTPUT UNITS │
- │ (Keyboard, Mouse, Display, Network, Storage) │
- └────────────────────────────────────────────────────────┘
- Core Pillars of the Von Neumann Architecture
The Stored-Program Concept: Instructions (code) and operands (data) are stored together in the same unified, read-write primary memory space . The CPU treats instructions and data identically as binary byte sequences; only the execution context distinguishes them.
Sequential Instruction Processing: Instructions are fetched and executed in strict sequential order from contiguous memory addresses, unless interrupted or redirected by a branch, jump, or conditional instruction.
Central Processing Unit (CPU): Comprises three primary sub-systems:
Arithmetic Logic Unit (ALU): The execution engine that executes elementary arithmetic operations (addition, subtraction, multiplication, division) and logical decisions (AND, OR, NOT, XOR, bitwise shifts, and numerical magnitude comparisons).
Control Unit (CU): The central nervous system of the CPU. It directs the internal traffic of data, orchestrates the multi-phase machine instruction cycle, and generates electrical synchronization control signals sent across the system bus.
High-Speed Internal Registers: Extremely fast, small physical storage circuits located directly on the CPU silicon die to hold operands, addresses, and intermediate computation states.
Crucial CPU Registers and Their Functions
Program Counter (PC): Holds the memory address of the next instruction scheduled to be fetched and executed. Automatically increments after each fetch cycle unless modified by a jump or subroutine call.
Memory Address Register (MAR): Holds the physical memory address currently being read from or written to over the address bus.
Memory Data Register (MDR) / Memory Buffer Register (MBR): Holds the actual data or instruction word fetched from memory, or waiting to be written into memory.
Instruction Register (IR): Holds the current binary instruction opcode fetched from memory while the Control Unit decodes it.
Accumulator (AC): A general-purpose working register that stores the immediate results of arithmetic and logical operations produced by the ALU.
Current Status / Flag Register: Contains individual status bits (flags) indicating the mathematical outcomes of the latest ALU operation (Zero Flag [Z], Carry Flag [C], Overflow Flag [V], Sign/Negative Flag [S]).
The System Bus Architecture
Communication between the CPU, primary memory, and peripheral controllers is mediated by three physical groups of parallel wires known collectively as the System Bus :
Data Bus: Bidirectional highway that carries actual data, operands, and instructions between the CPU and memory/devices. The width of the data bus (e.g., 32 bits, 64 bits) dictates how much data the CPU can transfer in a single cycle.
Address Bus: Unidirectional highway driven exclusively by the CPU to designate the specific physical memory location or I/O port being accessed. Crucial Math Formula: The width of the address bus determines the CPU's maximum addressable memory capacity. If an address bus has k k k lines (bits), it can address precisely 2 k 2^k 2 k distinct byte locations: 32-bit address bus ⟹ 2 32 bytes = 4,294,967,296 bytes = 4 GiB \text{32-bit address bus} \implies 2^{32} \text{ bytes} = 4{,}294{,}967{,}296 \text{ bytes} = 4 \text{ GiB} 32-bit address bus ⟹ 2 32 bytes = 4 , 294 , 967 , 296 bytes = 4 GiB 64-bit address bus ⟹ 2 64 bytes = 16 Exbibytes (EiB) \text{64-bit address bus} \implies 2^{64} \text{ bytes} = 16 \text{ Exbibytes (EiB)} 64-bit address bus ⟹ 2 64 bytes = 16 Exbibytes (EiB)
Control Bus: Bidirectional lines transmitting timing, status, and synchronization signals (Memory Read, Memory Write, I/O Read, Bus Request, Bus Acknowledge, Interrupt Requests [IRQ], and System Clock).
The Von Neumann Bottleneck: Because instructions and data must share the exact same physical bus to travel between primary memory and the CPU, throughput is physically capped by the memory bus bandwidth. The CPU frequently sits idle waiting for instructions or operands to arrive from relatively slow main memory. Modern processor designs mitigate this bottleneck through multi-level internal SRAM cache hierarchies , instruction prefetching, and pipelining.
4. Memory Hierarchy: Latency, Volatility, and Architecture
Computer storage is organized into a rigid hierarchical pyramid to balance three conflicting physical engineering realities: speed (latency) , cost per bit , and capacity . THE MEMORY HIERARCHY
- / \
- / REGISTERS \
- / (< 1 ns) \
- /────────────────\
- / L1/L2/L3 \
- / SRAM CACHE \
- / (1 - 10 ns) \
- /────────────────────────\
- / PRIMARY MAIN MEMORY \
- / DRAM (RAM) / ROM BIOS \
- / (10 - 50 ns) \
- /────────────────────────────────\
- / SECONDARY STORAGE \
- / Solid State (NVMe/SATA SSD) \
- / Hard Disk Drives (HDD) (ms) \
- /────────────────────────────────────────\
- / TERTIARY & CLOUD \
- / Magnetic Tape, Optical Storage, \
- / Cloud Archival Repositories \
- /────────────────────────────────────────────────\
- SPEED / COST INCREASES ▲ │ ▼ CAPACITY INCREASES
- Volatile vs. Non-Volatile Memory
Volatile Memory: Storage media that requires continuous electrical power to sustain its stored contents. When power is severed or interrupted, all stored binary data is instantaneously and irreversibly lost. Examples: CPU Registers, L1/L2/L3 Cache (SRAM), and System Main Memory (DRAM).
Non-Volatile Memory: Storage media that preserves its stored data indefinitely in the complete absence of electrical power. Examples: Read-Only Memory (ROM), Flash Memory (SSDs, USB thumb drives), magnetic hard drives, magnetic tapes, and optical discs.
Primary Random Access Memory (RAM): SRAM vs. DRAM
Competitive examinations frequently require candidates to contrast the two technological forms of volatile semiconductor RAM:
Architectural Attribute Static RAM (SRAM) Dynamic RAM (DRAM)
Storage Cell Construction Bistable latching circuitry (flip-flop) consisting of 4 to 6 transistors per bit. Single transistor and tiny microscopic capacitor per bit.
Electrical Refresh Requirement No refresh required. Holds state stably as long as power is applied. Requires continuous periodic refresh cycles (hundreds of times per second) because capacitors leak charge.
Access Speed / Latency Ultra-fast access time ( 0.5 to 5 nanoseconds ). Moderate access time ( 10 to 50 nanoseconds ).
Component Density Low component density (large physical silicon area per bit). Extremely high density (hundreds of millions of bits per chip).
Cost per Bit Highly expensive to manufacture. Highly economical and cost-effective.
Primary System Role CPU Cache Memory (L1, L2, L3 internal cache). Main System Memory (RAM) (DDR4, DDR5 modules).
Evolution of Read-Only Memory (ROM) and Firmware
Non-volatile primary memory stores the foundational startup firmware (BIOS / UEFI) required to perform the Power-On Self-Test (POST) and bootstrap the operating system from secondary storage into RAM:
Mask ROM (MROM): Hardwired at the semiconductor foundry during physical fabrication. The binary data pattern is etched permanently into the silicon mask. Completely unalterable and immune to reprogramming.
PROM (Programmable ROM): Manufactured in a blank state with tiny internal microscopic fusible links. The user or engineer writes data once using a high-voltage specialized device called a PROM programmer or "ROM burner" which permanently blows open specific fuses. One-Time Programmable (OTP) ; cannot be erased or rewritten once programmed.
EPROM (Erasable Programmable ROM): Distinguishable by a transparent circular quartz crystal window on top of the ceramic chip packaging. When exposed to intense high-frequency ultraviolet (UV) light for 20 to 30 minutes, photon energy excites electrons trapped on floating gates, erasing all stored data simultaneously. The chip can then be electrically reprogrammed. It must be physically removed from the circuit board to be erased.
EEPROM (Electrically Erasable Programmable ROM): Erased and reprogrammed using electrical voltage pulses without removing the chip from the computer motherboard. Crucially, EEPROM permits byte-level electrical modification , allowing individual configuration bytes to be updated without wiping the entire chip. It has finite write endurance (typically 100,000 to 1,000,000 write cycles).
Flash Memory: A modern high-density variation of EEPROM developed by Toshiba in the 1980s. Unlike traditional EEPROM which can erase byte-by-byte, Flash memory erases data in large multi-kilobyte blocks or sectors , achieving vastly higher density and write speeds. It represents the foundational technology powering Solid State Drives (SSDs), USB flash thumb drives, SD cards, and modern UEFI BIOS motherboard chips:
NOR Flash: Allows true random byte-level read access, making it ideal for storing processor execution code directly (Execute-in-Place / XIP firmware chips).
NAND Flash: Sacrifices byte-level random access in favor of high-density page/block sequential access, providing ultra-compact, high-capacity secondary storage for consumer SSDs and mobile devices.
5. Master Glossary of High-Yield ICT Abbreviations
The following comprehensive reference table compiles every foundational ICT abbreviation tested in state and national eligibility examinations, organized alphabetically with precise definitions:
Abbreviation Expanded Full Form Functional Definition and Exam Context
ALU Arithmetic Logic Unit The CPU execution sub-unit responsible for arithmetic calculations and boolean logic decisions.
ASCII American Standard Code for Information Interchange Foundational 7-bit character encoding standard representing 128 characters across digital hardware.
BIOS Basic Input/Output System Motherboard non-volatile firmware that initiates hardware initialization and POST during the boot sequence.
BLOB Binary Large Object A collection of binary data stored as a single entity in a database management system (e.g., images, multimedia).
CMOS Complementary Metal-Oxide-Semiconductor Battery-backed low-power semiconductor memory on the motherboard storing system date, time, and BIOS setup settings.
DBMS Database Management System Software suite enabling systematic creation, query execution, maintenance, and administrative control of databases.
DNS Domain Name System Distributed hierarchical internet naming database that translates human-readable hostnames into numeric IP addresses.
DRAM Dynamic Random Access Memory High-density volatile computer main memory utilizing capacitor-transistor cells requiring dynamic refresh cycles.
DVD-ROM Digital Versatile Disc – Read-Only Memory Optical storage medium holding 4.7 GB (single-layer) to 8.5 GB (dual-layer) of pre-recorded, unalterable data.
ENIAC Electronic Numerical Integrator and Computer The first programmable, general-purpose electronic digital computer, constructed at UPenn in 1945.
FTP File Transfer Protocol Application-layer client-server protocol (ports 20/21) utilized for transferring files between network hosts.
GUI Graphical User Interface Human-computer visual interaction paradigm utilizing windows, icons, menus, and pointers (WIMP).
HTML HyperText Markup Language The standard declarative markup language defining the structural layout and content elements of web pages.
HTTP HyperText Transfer Protocol Application-layer request-response protocol (port 80) governing data communication across the World Wide Web.
HTTPS HyperText Transfer Protocol Secure HTTP layered over an encrypted TLS/SSL cryptographic tunnel (port 443) ensuring privacy and integrity.
IC Integrated Circuit A miniaturized electronic semiconductor microchip containing interconnected transistors, resistors, and capacitors.
IP Internet Protocol Foundational network-layer protocol responsible for logical packet addressing and routing across internetworks.
ISP Internet Service Provider A commercial or public entity providing consumer and institutional access to the global Internet infrastructure.
JPEG Joint Photographic Experts Group Standardized lossy compression graphic format optimized for continuous-tone photographic still images.
LAN Local Area Network High-speed data communications network spanning a physically constrained area (office, classroom, laboratory).
MAC Media Access Control Unique 48-bit (6-octet) physical hardware address permanently assigned to a network interface card (NIC).
MAN Metropolitan Area Network High-speed network spanning an entire municipal city or large consolidated educational campus.
MIDI Musical Instrument Digital Interface Communications standard enabling electronic musical instruments, computers, and synthesizers to exchange control data.
MIME Multipurpose Internet Mail Extensions Internet standard extending email format to support non-ASCII text, binary attachments, audio, and video.
MODEM Modulator-Demodulator Hardware peripheral that converts digital computer signals into analog carrier signals and vice versa.
MP3 MPEG-1 Audio Layer III Standardized lossy audio compression format that drastically reduces file size while preserving acoustic fidelity.
OCR Optical Character Recognition Technology that converts scanned physical images of printed or handwritten text into machine-encoded editable text.
OMR Optical Mark Recognition Technology that detects the presence of pencil or ink marks on predefined paper forms (standard for competitive exam answer sheets).
OS Operating System Master system software that manages hardware resources, CPU scheduling, file storage, and peripheral access.
PDF Portable Document Format PostScript-derived file format developed by Adobe to represent documents independently of application software, OS, or hardware.
PNG Portable Network Graphics Raster-graphics file format supporting lossless data compression and variable alpha-channel transparency.
POST Power-On Self-Test Built-in diagnostic testing sequence executed by firmware immediately following system power-on before bootloader handoff.
PROM Programmable Read-Only Memory Blank memory chip that can be programmed exactly once using electrical fuse-burning equipment.
RAID Redundant Array of Independent Disks Storage virtualization architecture combining multiple physical drives into a single logical array for redundancy and performance.
RAM Random Access Memory High-speed volatile primary memory allowing read and write operations at uniform access speeds regardless of physical location.
RGB Red, Green, Blue Additive color model in which red, green, and blue light components are composited together to generate a visual color gamut.
RISC Reduced Instruction Set Computer CPU microarchitecture philosophy prioritizing a small, highly optimized set of simple instructions executing in a single cycle.
ROM Read-Only Memory Non-volatile primary storage media whose contents can be read by the CPU but cannot be altered during normal system operation.
SATA Serial Advanced Technology Attachment High-speed serial bus interface connecting host bus adapters to secondary mass storage devices (HDDs and SSDs).
SMTP Simple Mail Transfer Protocol Application-layer push protocol (port 25 / 587) governing the transmission of outgoing email across networks.
SSD Solid State Drive Non-volatile secondary storage device utilizing solid-state NAND flash memory, offering high IOPS and zero moving parts.
SRAM Static Random Access Memory Volatile semiconductor memory built with flip-flops that retains data without dynamic refresh, primarily used for CPU cache.
TCP/IP Transmission Control Protocol / Internet Protocol Core four-layer protocol suite governing universal end-to-end data communication and packet exchange across the Internet.
URL Uniform Resource Locator Standardized character string specifying the exact network address and transfer protocol used to retrieve a web resource.
USB Universal Serial Bus Industry standard establishing specifications for cables, connectors, and serial communication protocols for peripheral devices.
VGA Video Graphics Array Legacy analog video display standard and 15-pin connector introduced by IBM in 1987 supporting 640x480 resolution.
VoIP Voice over Internet Protocol Technology suite facilitating voice communications and multimedia sessions over Internet Protocol packet-switched networks.
WAN Wide Area Network Telecommunications network spanning a vast geographic scale, crossing municipal, regional, national, or global boundaries.
WORM Write Once, Read Many Storage media classification allowing data to be recorded exactly once while remaining permanently unalterable and readable.
WWW World Wide Web Globally interconnected informational system of hypertext documents and multimedia resources linked via HTTP and accessed through URLs.