Study guide
8.3 IEC 61131-3 Logic Implementation
NCEES PE Control Systems Engineering Exam Exam
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1 Introduction & Exam Overview
1.1 Current Exam Facts 1.2 Handbook, ISA-5.1, and IEC 61511 on Exam Day 1.3 CBT Strategy, AITs, Calculators, and Pacing
2 Process Measurement Sensors
2.1 Pressure, Level, and Temperature Sensors 2.2 Flow, Counter, and Motion Sensors 2.3 Analytical Instruments and Sampling Systems
3 Specialty Sensors and Characteristics
3.1 Fire and Gas Detectors 3.2 Machinery Monitoring and Protection 3.3 Sensor Characteristics: Accuracy, Calibration, and Dynamics
4 Selection, Installation, and Primary Calculations
4.1 Sensor Selection and Material Compatibility 4.2 Sensor Installation Details and Drawings 4.3 Flow Calculations 4.4 Level Calculations
5 Conversions, Thermowells, and Checkout
5.1 Process Measurement Unit Conversions 5.2 Thermowell Design and Wake Frequency 5.3 Sensor Testing and Commissioning
6 Drawings, Dynamics, and PID
6.1 P&IDs, Loop Diagrams, and ISA-5.1 Symbology 6.2 Process Dynamics and Loop Response 6.3 Feedback Control and PID
7 Advanced, Discrete, and Process Applications
7.1 Feedforward, Cascade, Ratio, Override, and Split-Range 7.2 Discrete and Sequential Control 7.3 Control of Common Process Equipment
8 HMI, Alarms, Logic, and Architecture
8.1 HMI, Displays, and Control-Room Layout 8.2 Alarm Management 8.3 IEC 61131-3 Logic Implementation 8.4 DCS, PLC, SCADA Architecture and Interfaces
9 Capacity, Testing, and Cybersecurity
9.1 Capacity, Availability, Heat Load, Power, and Environment 9.2 FAT, IST, SAT, and Commissioning 9.3 Performance Monitoring and Management of Change 9.4 Control-System Cybersecurity
10 Valve Type, Trim, Sizing, and Actuators
10.1 Valve Types and Materials 10.2 Valve Trim, Leakage Class, and Characteristics 10.3 Valve Sizing, Pressure Drop, and Split-Range 10.4 Actuators and Failure Modes
11 Fluid Dynamics, Accessories, and Relief Types
11.1 Cavitation, Flashing, Choked Flow, and Noise 11.2 Valve Accessories and Installation 11.3 Pressure-Relieving Device Types and Installation 11.4 Pressure-Relieving Device Calculations
12 Motors, Solenoids, Regulators, and Checkout
12.1 Motor Starters, VSDs, and Soft Starters 12.2 Solenoid Valves and Relays as Final Elements 12.3 Self-Regulating Devices 12.4 Final Element Testing and Commissioning
13 Signal Types and Conversion
13.1 Analog and Discrete Signal Types 13.2 Buses, Topologies, and Digital Protocols 13.3 Signal Conversion, I/P, Splitters, and Bit Precision
14 Hazardous Areas, Power, and Circuits
14.1 Hazardous-Area Methods and Intrinsic Safety 14.2 Power, Grounding, Segregation, and EMI 14.3 Two-Wire, Four-Wire, and Loop Calculations
15 Media and Network Architecture
15.1 Transmission Media: Copper, Fiber, Wireless 15.2 TCP/IP, OPC, Addressing, and Architectures 15.3 OPC, Network Addressing, and Segmentation
16 Lifecycle and Risk Allocation
16.1 IEC 61511 Lifecycle Structure and Phases 16.2 Hazard and Risk Assessment 16.3 LOPA, IPLs, and SIF Identification
17 SRS, Design, and SIL Calculations
17.1 Safety Requirements Specification 17.2 SIS Design, Device Selection, and Constraints 17.3 SIL Calculations and Formulas
18 SAT, Proof Testing, and MOC
18.1 Installation, Commissioning, Validation, and SAT 18.2 Operation, Proof Testing, Demands, and Bypasses 18.3 Modification, Decommissioning, and MOC
8.3 IEC 61131-3 Logic Implementation
Key Takeaways Explain This Topic AI
NCEES lists limited-variability IEC 61131-3 languages for DCS/PLC: ladder, function blocks, sequential function charts, structured text, and (legacy) instruction list.
Match language to job: interlocks in LD or FBD, batch/state machines in SFC, calculations and data handling in ST. Do not dump vendor syntax on the exam.
Instruction List was deprecated in IEC 61131-3:2013 and removed in the 2025 fourth edition. New work uses ST, LD, FBD, or SFC even if the NCEES example list still names IL.
Scan time, watchdogs, forcing, and first-out latches are how unexpected behavior is created and diagnosed. A force left in place is a lying I/O image.
SFC that waits forever on a transition is incomplete. Every step that can fail to complete needs a timeout/abort path that drives outputs to a defined safe or hold state.
Last updated: August 2026
Limited-variability languages for DCS and PLC
NCEES 2.D covers logic implementation , configuration/programming, exception handling, and diagnosis, including IEC 61131-3 ladder diagrams, function blocks, sequential function charts, and structured text. Instruction list is an older IEC 61131-3 language that still appears in some plants; do not assume it is the preferred 2027 answer. Limited variability language (LVL) means the programmer assembles predefined constructs (contacts, coils, certified function blocks, SFC steps) rather than writing arbitrary C/C++ ( full variability language, FVL ).
IEC 61511-1:2018 (supplied on the exam) uses that LVL/FVL distinction for SIS application programming . For BPCS DCS/PLC work, LVL is still the normal PE answer: you are configuring and programming with standard languages, not inventing a new compiler. Do not put safety-instrumented logic only in an HMI script or an uncertified general-purpose program and call it a SIF.
Configuration versus programming :
Configuration — I/O assignment, task/scan rates, redundancy roles, alarm attributes, HMI tag binds, controller-to-controller publications.
Programming — the POU body: what Boolean, analog, or sequence actually runs.
Unexpected behavior is as often a configuration error (wrong task, retained memory, force, wrong I/O channel) as a “bug in the rung.”
This section teaches concepts . It does not dump vendor dialects (Siemens SCL, Rockwell ST, Emerson control modules). The exam is language-class judgment, not a brand editor.
The language set (and the IL trap)
Language Form Strength Typical fit Exam trap
Ladder diagram (LD) Graphical contacts/coils Online Boolean visibility; electricians and discrete interlocks Permissives, motor start/stop, hard interlocking Writing PID and matrix math as a wall of rungs
Function block diagram (FBD) Graphical blocks and wires Analog/signal flow; reusable PID, filters, voter blocks Continuous loops, 2oo3 voters shown as blocks Hiding a trip in an undocumented custom block with no first-out
Sequential function chart (SFC) Steps, transitions, actions States are first-class; parallel branches Batch, startup/shutdown, packaging cycles Happy-path only; no timeout if a transition never goes true
Structured text (ST) Textual Pascal-like Math, arrays, recipes, string/comms, compact algorithms Scaling, compensation, data movement Unreadable nested logic that should have been LD/FBD for diagnosis
Instruction list (IL) Assembler-like mnemonics Legacy compactness Maintain old code only Treating IL as the preferred new language
IEC 61131-3:2013 (third edition) deprecated IL . IEC 61131-3:2025 (fourth edition) removed it. The NCEES example list still names IL because the specification text has been stable since 2019. For new logic, answer ST/LD/FBD/SFC . For existing IL, the PE job is understand-and-migrate, not write more IL.
You may mix languages: an SFC step action can call an LD interlock POU and an ST calculation. Each POU body is one language; the project is not.
When each language fits
Interlock / permissive (“both seal-oil pumps stopped AND compressor running → trip”). Start in LD or FBD . The path is visible during online diagnosis (rung highlight or block values). ST IF trees that pack twelve interlocks into one statement fail FAT when a technician cannot see which contact is false.
Continuous analog. FBD (or DCS function-block composites) for PID, lead-lag, selectors, and tracking. ST for the ugly equation inside a block, not for the entire plant as a 4,000-line script.
Batch / sequential / state machine. SFC (or an explicit state machine). ISA-88 phase logic maps cleanly onto steps. Do not encode a 12-state startup as a ladder “seal-in” maze unless the plant standard forbids SFC and you document the state bits.
Calculations. ST : density compensation, valve characterization, moving averages, recipe indexing. Keep the results in named variables that FBD/LD can consume.
Scan time, watchdog, forcing, first-out
A typical cyclic controller scan is: read inputs → execute programs in task order → write outputs. Scan time is how long that cycle takes. If analog loops or anti-surge need 50–200 ms class updates, a 500 ms overloaded task is a design error, not a mystery.
Watchdog: if scan exceeds a configured limit, the CPU takes a fault/safe response (hold last, de-energize, switch to backup—product-specific, but the idea is “the program is no longer timely”). A watchdog trip during a flood of unoptimized ST loops is a real PE diagnosis.
Forcing: an engineering override of the I/O image. Used in FAT/SAT to simulate a transmitter. A force left in production makes interlocks look healthy while the field is not. Forces must be visible , authorized , and cleared before handover. They are not an HMI color.
First-out: a latch of the first trip cause in a group. After twenty outputs drop, the latch still says “high vibration,” not “everything is bad.” Implement it in LD/FBD as a latched bit that only a reset (after the process is safe) clears. SFC can record the step that failed; that is first-out for sequences.
Diagnosing unexpected behavior
Work this list before rewriting logic:
Force still on or simulation mode left enabled.
Wrong task — a fast interlock sitting in a slow program; a race between two tasks writing the same output.
Scan overrun / watchdog — logic that “sometimes” misses a pulse (aliasing of a discrete, named in NCEES discrete-control examples).
Retained versus non-retained memory after power cycle—sequence thinks it is still in FILL.
Communication timeout treated as a frozen good PV (fail-last versus fail-safe).
SFC stuck — transition false forever; no exception path.
First-out not latched — operators argue about which trip was first.
Worked example: SFC exception handling when a transition never goes true
Given. Batch reactor R-12 FILL step: action opens inlet valve FV-1201. Transition to MIX is LT-1201 >= 85% (high-level). No step timer. Structured text inside the step only sets the valve.
Fault. LT-1201 fails low (open thermocouple equivalent for a level probe, or a 4 mA freeze). The transition never goes true . FV-1201 stays open. The tank overflows. The SFC still shows FILL as the active step—technically “working as coded.”
What was missing. Exception handling on that step:
A watchdog / maximum step time (for example, FILL must complete in 8 minutes based on known inlet flow and volume). When the timer expires, a fault transition fires even if level is not 85%.
The fault step closes FV-1201 , inhibits MIX, and alarms “FILL timeout — level not confirmed” (this is an alarm: action is stop feed and investigate).
Optionally a second transition on LT-1201 bad quality so you do not wait the full eight minutes if the transmitter already declared fail.
After abort: a defined HOLD/RESET path (drain, inert, wait for operator reset). Do not auto-retry FILL with the valve still open.
Languages around the chart. The timeout comparison can be ST or a TON in FBD; the structure is still SFC. The inlet-valve interlock “high-high independent LS-1202 trips close” should remain LD/FBD independent of the SFC so a stuck chart cannot disable the hard interlock. That is the same independence idea IEC 61511-1 enforces for SIS versus BPCS—here applied at the BPCS layering level: sequence is not the only protection.
Exam trap. “Use a faster scan so the failed transmitter will eventually go true.” A failed-low PV does not become true because you scan harder. “Force the high-level input” is a FAT shortcut, not a production exception handler.