9.2 FAT, IST, SAT, and Commissioning

NCEES PE Control Systems Engineering Exam Exam

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1 Introduction & Exam Overview

1.1 Current Exam Facts 1.2 Handbook, ISA-5.1, and IEC 61511 on Exam Day 1.3 CBT Strategy, AITs, Calculators, and Pacing

2 Process Measurement Sensors

2.1 Pressure, Level, and Temperature Sensors 2.2 Flow, Counter, and Motion Sensors 2.3 Analytical Instruments and Sampling Systems

3 Specialty Sensors and Characteristics

3.1 Fire and Gas Detectors 3.2 Machinery Monitoring and Protection 3.3 Sensor Characteristics: Accuracy, Calibration, and Dynamics

4 Selection, Installation, and Primary Calculations

4.1 Sensor Selection and Material Compatibility 4.2 Sensor Installation Details and Drawings 4.3 Flow Calculations 4.4 Level Calculations

5 Conversions, Thermowells, and Checkout

5.1 Process Measurement Unit Conversions 5.2 Thermowell Design and Wake Frequency 5.3 Sensor Testing and Commissioning

6 Drawings, Dynamics, and PID

6.1 P&IDs, Loop Diagrams, and ISA-5.1 Symbology 6.2 Process Dynamics and Loop Response 6.3 Feedback Control and PID

7 Advanced, Discrete, and Process Applications

7.1 Feedforward, Cascade, Ratio, Override, and Split-Range 7.2 Discrete and Sequential Control 7.3 Control of Common Process Equipment

8 HMI, Alarms, Logic, and Architecture

8.1 HMI, Displays, and Control-Room Layout 8.2 Alarm Management 8.3 IEC 61131-3 Logic Implementation 8.4 DCS, PLC, SCADA Architecture and Interfaces

9 Capacity, Testing, and Cybersecurity

9.1 Capacity, Availability, Heat Load, Power, and Environment 9.2 FAT, IST, SAT, and Commissioning 9.3 Performance Monitoring and Management of Change 9.4 Control-System Cybersecurity

10 Valve Type, Trim, Sizing, and Actuators

10.1 Valve Types and Materials 10.2 Valve Trim, Leakage Class, and Characteristics 10.3 Valve Sizing, Pressure Drop, and Split-Range 10.4 Actuators and Failure Modes

11 Fluid Dynamics, Accessories, and Relief Types

11.1 Cavitation, Flashing, Choked Flow, and Noise 11.2 Valve Accessories and Installation 11.3 Pressure-Relieving Device Types and Installation 11.4 Pressure-Relieving Device Calculations

12 Motors, Solenoids, Regulators, and Checkout

12.1 Motor Starters, VSDs, and Soft Starters 12.2 Solenoid Valves and Relays as Final Elements 12.3 Self-Regulating Devices 12.4 Final Element Testing and Commissioning

13 Signal Types and Conversion

13.1 Analog and Discrete Signal Types 13.2 Buses, Topologies, and Digital Protocols 13.3 Signal Conversion, I/P, Splitters, and Bit Precision

14 Hazardous Areas, Power, and Circuits

14.1 Hazardous-Area Methods and Intrinsic Safety 14.2 Power, Grounding, Segregation, and EMI 14.3 Two-Wire, Four-Wire, and Loop Calculations

15 Media and Network Architecture

15.1 Transmission Media: Copper, Fiber, Wireless 15.2 TCP/IP, OPC, Addressing, and Architectures 15.3 OPC, Network Addressing, and Segmentation

16 Lifecycle and Risk Allocation

16.1 IEC 61511 Lifecycle Structure and Phases 16.2 Hazard and Risk Assessment 16.3 LOPA, IPLs, and SIF Identification

17 SRS, Design, and SIL Calculations

17.1 Safety Requirements Specification 17.2 SIS Design, Device Selection, and Constraints 17.3 SIL Calculations and Formulas

18 SAT, Proof Testing, and MOC

18.1 Installation, Commissioning, Validation, and SAT 18.2 Operation, Proof Testing, Demands, and Bypasses 18.3 Modification, Decommissioning, and MOC

9.2 FAT, IST, SAT, and Commissioning

Key Takeaways Explain This Topic AI

FAT proves vendor hardware and software against simulated I/O; it will not catch impulse-line slope, shield grounds, or real valve stroke time.

IST proves cross-package interfaces (DCS to SIS, compressor PLC, analyzers) that a single-system FAT can miss.

SAT proves installation and real devices; commissioning adds live-process tuning, first-feed, and turnover to operations.

Sequence timers validated on a one-scan simulated actuator fail when the real valve takes many seconds to stroke.

Loop checks prove the signal path; logic tests prove Boolean; sequence tests prove steps and timers; fail-safe tests remove energy and watch the designated position.

Last updated: August 2026

You cannot inspect quality into a DCS after first feed. Knowledge area 2.F expects you to know what each test proves and, just as important, what it cannot prove. The exam loves a stem where a sequence passed in the shop and then failed on the unit—usually because the shop never saw the field.

Factory acceptance test (FAT)

FAT happens at the vendor (or integrator) facility. The system is on a shop floor. I/O is simulated, or wired to a test panel of switches, lamps, and a simulation computer. FAT is the right place to prove:

I/O configuration against the I/O list (tag, type, range, fail direction).

Control configuration against the narrative and cause-and-effect matrix.

Graphics against P&ID tags and the alarm philosophy.

CPU and network redundancy failover of the architecture that is actually in the cabinets.

Historian collection of those tags, time sync, and user accounts.

System diagnostics the vendor shipped: I/O channel faults, controller status, network storms the shop can generate.

FAT does not prove field installation. It will not catch an impulse line that slopes back toward the transmitter so condensate collects. It will not catch tap location, heat tracing, cable-tray fill, shield grounds at one end only, classified-area gland sealing, real actuator bench set, packing friction, actual process lags, site fiber loss, or wireless spectrum at the unit. If the stem is a wet-leg or slope problem after a clean FAT, the answer is not 'FAT was skipped.' The answer is that FAT never saw the pipe.

Integrated system test (IST)

IST (sometimes staged as an integrated FAT) puts more than one subsystem on the same floor: DCS plus SIS, compressor PLC, analyzer shelter, custody skid, maybe an operator-training simulator. IST proves interface contracts that a single-system FAT can miss: permissive bits, watchdog or heartbeat timing, sequence-of-events order across systems, third-party Modbus or OPC maps, and which system is time master. A DCS FAT alone will not find that the compressor PLC expects a 200 ms heartbeat while the DCS sends a 1 s pulse. IST is still usually a simulated or packaged process. It still will not catch impulse-line slope or a sticky valve on the pipe rack.

Site acceptance test (SAT) and commissioning

SAT is at the plant after mechanical completion, or after a defined subset of loops is landed. I/O is real, or at least real wiring to junction boxes and real field devices on the loops being tested. SAT proves installation integrity: loop checks, communications over plant fiber, real valve stroke, real trip solenoids, grounding, and that the cabinets still run within temperature after site power and HVAC are the real ones. SAT still may not include hydrocarbons, every rare interlock combination, or long-term reliability. A passed SAT is a contractual gate, not a promise that the unit will never surprise you.

Commissioning is broader than SAT. It includes loop checkout, water batch or inert commissioning, first feed, performance tuning , punchlist closeout, as-built drawings, and turnover to operations. SAT asks 'does the installed system match the spec?' Commissioning asks 'can this plant run?' Tuning a level loop on water and then on a foaming hydrocarbon are different jobs; only commissioning sees the second.

Loop, logic, sequence, and fail-safe tests

These four tests get mixed on the exam. Keep the energy path in mind.

A loop check proves the signal path: field device through wiring and I/O to the faceplate, and output back to the actuator—range, polarity, engineering units, and fail direction of the signal . You can loop-check at SAT with the process isolated.

A logic test proves Boolean: permissives, interlocks, cause-and-effect. FAT with simulated I/O is an excellent logic test. It still assumes the simulated input is the real process.

A sequence test proves steps, transitions, timers, holds, aborts, and restarts (SFC, batch, compressor start). If a transition is 'wait 2 s for the valve to open,' the test is only as honest as the actuator model.

A fail-safe test removes energy—air, hydraulic pressure, electrical power, or communication—and confirms the device goes to the designated fail position and that the logic treats the loss correctly. Watching a faceplate while you type a 50% PV is not a fail-safe test.

System diagnostics belong in every stage: channel fault bits at FAT, network error counters at IST, grounding and noise at SAT, and drift or sticky-valve signatures after startup (the next section).

Worked example — FAT pass, SAT fail on stroke time

A compressor anti-surge recycle sequence is tested at FAT. The analog output drives a simulated valve that goes 0–100% in one controller scan. A 2 s timer expires, the sequence declares the recycle valve open, and the load/unload steps continue. The cause-and-effect and the SFC both pass. At SAT the real 8-inch valve, with a pneumatic actuator and a booster that is not as fast as the datasheet implied, takes about 12 s to stroke. The 2 s timer times out while the valve is still mostly shut. The machine either trips on a sequence fault or is left without recycle when a surge approaches.

The logic was not 'wrong' in the Boolean sense. The timing basis was wrong. FAT proved the sequence against a near-instant actuator. SAT revealed process dead time plus real stroke time. The professional fix is not to blame SAT. Use valve position feedback (or a generous timer plus feedback) as the transition, include actual stroke plus margin in any backup timer, and put real stroke tests in the SAT procedure—not only simulated I/O in the shop. The same pattern shows up on ESD trip solenoids, MOV stroke limits, and damper drives.

Work additional FAT/SAT judgment items in the free PE Control Systems practice questions .

Stage Where Typical I/O Proves Does not prove

FAT Vendor / integrator shop Simulated or test panel Logic, graphics, config, shop redundancy, many diagnostics Field install, impulse-line slope, real stroke, site fiber

IST Staging floor Simulated or package skids Cross-system interfaces, heartbeats, SOE order, maps Site wiring, process dynamics, classified-area fittings

SAT Plant Real devices or real wiring Installation, loop checks, real comms, real stroke Every process case, long-term reliability, first-feed dynamics

Commissioning Plant, live or first process Real process Tuning, actual dynamics, procedures, turnover That no future MOC will be needed

Exam traps: calling FAT a field-installation proof; treating IST as optional when packages handshake; using a simulated one-scan valve to validate a timed sequence; calling a faceplate PV entry a fail-safe test.