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7.3 Computer Fundamentals, Programming & Data Logic
PRC Registered Electrical Engineer REE
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1 Chapter 1: Overview, RA 7920 & Electrical Engineering Ethics
1.1 PRC Board of Electrical Engineering & REE Examination Overview 1.2 Republic Act No. 7920 (New Electrical Engineering Law) & License Classes 1.3 Code of Ethics & Professional Practice for Electrical Engineers
2 Chapter 2: Math — Algebra, Trig & Geometry
2.1 Algebraic Equations, Polynomials & Complex Numbers 2.2 Trigonometry — Identities, Triangles & Spherical Trig 2.3 Analytic & Solid Geometry
3 Chapter 3: Engineering Mathematics — Calculus & Differential Equations
3.1 Differential Calculus, Limits, Derivatives & Applications 3.2 Integral Calculus, Integration Techniques & Area/Volume Applications 3.3 Ordinary Differential Equations & Initial-Value Problems
4 Chapter 4: Engineering Mathematics — Advanced Math & Transform Methods
4.1 Laplace Transforms, Inverse Transforms & Circuit Applications 4.2 Fourier Series, Fourier Transforms & Frequency-Domain Analysis 4.3 Vector Analysis, Linear Algebra, Matrices & Complex Analysis
5 Chapter 5: Engineering Mathematics — Probability, Statistics & Engineering Data Analysis
5.1 Probability Theory, Counting Techniques & Bayes' Theorem 5.2 Engineering Data Analysis I — Descriptive Statistics & Probability Distributions 5.3 Engineering Data Analysis II — Confidence Intervals, Hypothesis Testing & Regression
6 Chapter 6: Engineering Mathematics — Numerical Methods & Analysis
6.1 Numerical Root-Finding & Solution of Linear Systems 6.2 Interpolation, Numerical Integration & Numerical Solution of ODEs
7 Chapter 7: ESAS — Physics, Chemistry & Computer Fundamentals
7.1 Physics for Engineers 7.2 General Chemistry & Materials Science 7.3 Computer Fundamentals, Programming & Data Logic 7.4 Logic Circuits, Switching Theory & Microprocessor Systems
8 Chapter 8: ESAS — Mechanics & Thermal-Fluid Engineering
8.1 Engineering Mechanics — Statics & Dynamics 8.2 Strength of Materials & Mechanics of Deformable Bodies 8.3 Thermal-Fluid Engineering — Thermodynamics & Fluid Mechanics
9 Chapter 9: ESAS — Engineering Economics, Management & Contracts
9.1 Engineering Economics & Depreciation 9.2 Engineering Management & Ethics 9.3 Philippine Electrical Engineering Law, Code & Contracts 9.4 Technopreneurship 101 & Management of Engineering Projects
10 Chapter 10: PEC 1 — Safety, Sizing & Protection
10.1 PEC Fundamentals, Safety Standards & Grounding/Bonding 10.2 Conductor Sizing, Ampacity Adjustment & Voltage Drop 10.3 Overcurrent Protection, Branch Circuit & Feeder Sizing 10.4 Basic Occupational Safety & Health (BOSH) and Electrical Safety Standards
11 Chapter 11: PEC 1 & 2 — Equipment & Utility Systems
11.1 PEC Equipment Installation & Wiring Methods 11.2 Utility Systems, Transformers & Switchgear 11.3 Special Occupancies & Hazardous Locations
12 Chapter 12: Electrical Professional — DC & AC Circuit Fundamentals
12.1 DC Circuit Analysis & Network Theorems 12.2 Single-Phase AC Circuits & Phasor Analysis 12.3 Balanced & Unbalanced Three-Phase AC Circuits
13 Chapter 13: Electrical Professional — EM Fields & Transients
13.1 Electrostatics, Magnetostatics & Maxwell's Equations 13.2 Electromagnetic Waves & Transmission Line Fields 13.3 First-Order & Second-Order Circuit Transients
14 Chapter 14: Electrical Professional — Electronics, Industrial Electronics & Communications
14.1 Electronics 1 & 2 — Semiconductor Devices & Analog Circuits 14.2 Electrical Apparatus & Devices — Industrial Electronics & Power Converters 14.3 Fundamentals of Electronic Communications
15 Chapter 15: Electrical Professional — Transformers & DC Machines
15.1 Single-Phase & Three-Phase Transformers 15.2 Transformer Connections & Special Transformers 15.3 DC Generators & DC Motors
16 Chapter 16: Electrical Professional — AC Synchronous & Induction Machinery
16.1 Synchronous Generators (Alternators) 16.2 Synchronous Motors & Special AC Machines 16.3 Three-Phase & Single-Phase Induction Motors
17 Chapter 17: Electrical Professional — Power Plants & Energy Conversion
17.1 Hydroelectric, Thermal & Combined Cycle Power Plants 17.2 Renewable Energy Systems & Geothermal Power Plants 17.3 Power Plant Economics, Load Curves & Energy Conversion
18 Chapter 18: Electrical Professional — Transmission & Distribution
18.1 Transmission Line Parameters & Performance Models 18.2 Mechanical Overhead Line Design, Underground Cables & Insulators 18.3 Distribution Systems, Substation Layouts & Power Flow Control
19 Chapter 19: Electrical Professional — Power System Analysis
19.1 The Per-Unit System, Base Conversion & Impedance Diagrams 19.2 Symmetrical Components & Unbalanced Fault Analysis 19.3 Load Flow, Economic Dispatch & Power System Stability
20 Chapter 20: Electrical Professional — Protection, Control, Instrumentation & Illumination
20.1 Power System Protection & Protective Relaying 20.2 Industrial Motor Control, Logic Circuits & PLC Automation 20.3 Electrical Instrumentation, Transducers & Measurement Systems 20.4 Illumination Engineering, Lighting Design & Photometrics 20.5 Feedback Control Systems & Research Methods
7.3 Computer Fundamentals, Programming & Data Logic
Key Takeaways Explain This Topic AI
Von Neumann architecture comprises CPU (ALU, CU, Registers), memory unit (RAM/ROM), and I/O interface connected via system buses.
Signed integers use 2's complement representation with range [ − 2 n − 1 , 2 n − 1 − 1 ] [-2^{n-1}, 2^{n-1}-1] [ − 2 n − 1 , 2 n − 1 − 1 ] ; IEEE 754 single precision stores 32-bit floats using 1 sign bit, 8 exponent bits, and 23 mantissa bits.
De Morgan's Laws ( A + B ‾ = A ˉ ⋅ B ˉ \overline{A+B} = \bar{A}\cdot\bar{B} A + B = A ˉ ⋅ B ˉ and A ⋅ B ‾ = A ˉ + B ˉ \overline{A\cdot B} = \bar{A} + \bar{B} A ⋅ B = A ˉ + B ˉ ) and Karnaugh maps simplify Boolean logic expressions for digital hardware design.
High-level programming utilizes control flow constructs (sequence, selection, iteration) and modular functions to execute algorithm logic efficiently.
Computer networks utilize the 7-layer OSI model and IPv4/IPv6 addressing to structure digital communications.
Last updated: August 2026
7.3 Computer Fundamentals, Programming & Data Logic
Computer Fundamentals and Computer Programming constitute a dedicated portion of the ESAS subject area in the REE Licensure Examination. Electrical engineers regularly interface with microcontrollers, PLCs, embedded control systems, digital signal processors, and software algorithms.
- 1. Computer Hardware & Systems Architecture
- The Von Neumann Architecture
Most modern computing systems are based on the Von Neumann Architecture , which features stored programs where instructions and data share the same memory space. VON NEUMANN SYSTEM ARCHITECTURE
- ┌─────────────────────────────────────────────────────────────┐
- │ CENTRAL PROCESSING UNIT (CPU) │
- │ ┌─────────────────────────┐ ┌─────────────────────────┐ │
- │ │ Arithmetic Logic Unit │ │ Control Unit │ │
- │ │ (ALU) │ │ (CU) │ │
- │ └────────────┬────────────┘ └────────────┬────────────┘ │
- │ │ ┌───────────────────┐ │ │
- │ └───►│ CPU Registers (PC,│◄───┘ │
- │ │ IR, MAR, MDR, ACC)│ │
- │ └───────────────────┘ │
- └──────────────────────────────┬──────────────────────────────┘
- │ System Bus (Data, Address, Control)
- ┌──────────────────────────────┴──────────────────────────────┐
- │ MAIN MEMORY (RAM / ROM) │
- └──────────────────────────────┬──────────────────────────────┘
- │ I/O Bus
- ┌──────────────────────────────┴──────────────────────────────┐
- │ INPUT / OUTPUT (I/O) DEVICES │
- └─────────────────────────────────────────────────────────────┘
- Key CPU Components & Memory Hierarchy
Arithmetic Logic Unit (ALU): Performs integer arithmetic (add, subtract) and bitwise logical operations (AND, OR, XOR, shift).
Control Unit (CU): Fetches instructions from memory, decodes operation codes, and generates timing signals.
Registers: High-speed storage inside CPU (e.g., Program Counter PC , Instruction Register IR , Accumulator ACC ).
Memory Hierarchy: Registers (Fastest/Smallest) → \rightarrow → L1/L2/L3 Cache → \rightarrow → Main Memory (RAM) → \rightarrow → Secondary Storage (NVMe/SSD/HDD) (Slowest/Largest).
- 2. Number Systems & Data Representation
- Positional Radix Systems
- Number System Radix (Base) Valid Digits / Symbols Example Representation
- Binary 2 0, 1 1011.01 2 1011.01_2 1011.0 1 2
- Octal 8 0, 1, 2, 3, 4, 5, 6, 7 15.2 8 15.2_8 15. 2 8
- Decimal 10 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 11.25 10 11.25_{10} 11.2 5 10
- Hexadecimal 16 0–9, A(10), B(11), C(12), D(13), E(14), F(15) B .4 16 \text{B}.4_{16} B . 4 16
- 2's Complement Signed Integer Representation
To represent negative integers in binary using n n n bits:
Write the n n n -bit magnitude binary representation of the positive number.
Invert all bits ( 0 → 1 0 \rightarrow 1 0 → 1 and 1 → 0 1 \rightarrow 0 1 → 0 ) to form the 1's complement .
Add 1 to the 1's complement to yield the 2's complement .
Representable Range for n n n bits: − 2 n − 1 ≤ X ≤ 2 n − 1 − 1 -2^{n-1} \le X \le 2^{n-1} - 1 − 2 n − 1 ≤ X ≤ 2 n − 1 − 1
For 8 bits ( n = 8 n=8 n = 8 ): Range is − 128 -128 − 128 to + 127 +127 + 127 .
For 16 bits ( n = 16 n=16 n = 16 ): Range is − 32 , 768 -32,768 − 32 , 768 to + 32 , 767 +32,767 + 32 , 767 .
IEEE 754 Floating-Point Standard (Single Precision 32-bit) Value = ( − 1 ) S × 1. M × 2 E − 127 \text{Value} = (-1)^S \times 1.M \times 2^{E - 127} Value = ( − 1 ) S × 1. M × 2 E − 127
- Sign Bit ( S S S ): Bit 31 (1 bit, 0 = Positive, 1 = Negative)
- Biased Exponent ( E E E ): Bits 30–23 (8 bits, Bias = 127)
- Mantissa / Significand ( M M M ): Bits 22–0 (23 bits, implicit leading 1)
- 3. Boolean Algebra & Logic Gates
Digital logic circuits implement Boolean functions using basic and universal logic gates.
Basic Logic Gate Summary
- Gate Type Boolean Expression Truth Table Output ( A , B A, B A , B ) Note
- AND Y = A ⋅ B Y = A \cdot B Y = A ⋅ B 1 only if A = 1 A=1 A = 1 AND B = 1 B=1 B = 1 Series contacts
- OR Y = A + B Y = A + B Y = A + B 1 if A = 1 A=1 A = 1 OR B = 1 B=1 B = 1 Parallel contacts
- NOT Y = A ˉ Y = \bar{A} Y = A ˉ Inverts input bit Inverter
NAND Y = A ⋅ B ‾ Y = \overline{A \cdot B} Y = A ⋅ B 0 only if A = 1 A=1 A = 1 AND B = 1 B=1 B = 1 Universal Gate
NOR Y = A + B ‾ Y = \overline{A + B} Y = A + B 1 only if A = 0 A=0 A = 0 AND B = 0 B=0 B = 0 Universal Gate
XOR Y = A ⊕ B = A B ˉ + A ˉ B Y = A \oplus B = A\bar{B} + \bar{A}B Y = A ⊕ B = A B ˉ + A ˉ B 1 if inputs are DIFFERENT Odd parity check
XNOR Y = A ⊕ B ‾ = A B + A ˉ B ˉ Y = \overline{A \oplus B} = AB + \bar{A}\bar{B} Y = A ⊕ B = A B + A ˉ B ˉ 1 if inputs are EQUAL Equivalence check
- Key Boolean Algebra Laws
- De Morgan's First Law: A + B ‾ = A ˉ ⋅ B ˉ \overline{A + B} = \bar{A} \cdot \bar{B} A + B = A ˉ ⋅ B ˉ
- De Morgan's Second Law: A ⋅ B ‾ = A ˉ + B ˉ \overline{A \cdot B} = \bar{A} + \bar{B} A ⋅ B = A ˉ + B ˉ
Absorption Law: A + ( A ⋅ B ) = A and A ⋅ ( A + B ) = A A + (A \cdot B) = A \quad \text{and} \quad A \cdot (A + B) = A A + ( A ⋅ B ) = A and A ⋅ ( A + B ) = A
Consensus Theorem: A B + A ˉ C + B C = A B + A ˉ C A B + \bar{A} C + B C = A B + \bar{A} C A B + A ˉ C + BC = A B + A ˉ C
- 4. Structured Programming & Algorithm Logic
- Control Flow Structures
High-level languages (such as C, C++, Python) structure execution logic into three fundamental patterns:
Sequence: Step-by-step execution of linear statements.
Selection (Branching): Decision-making via if-else or switch-case statements based on conditional boolean evaluation.
Iteration (Looping): Repeating code blocks via for , while , or do-while constructs.
OSI 7-Layer Networking Reference Model
- Layer Layer Name Core Function / Protocol
- 7 Application HTTP, HTTPS, FTP, SMTP, DNS
- 6 Presentation Data encryption, SSL/TLS, compression, ASCII encoding
- 5 Session Session establishment, management, teardown (RPC, NetBIOS)
- 4 Transport End-to-end reliability, port addressing, TCP (connection-oriented), UDP
- 3 Network Logical IP addressing, packet routing (IPv4, IPv6, ICMP, Routers)
- 2 Data Link Physical MAC addressing, framing, error detection (Ethernet, Switches)
- 1 Physical Transmission of raw bit streams over physical medium (Cables, Fiber, Hubs)
- Solved Practice Examples
- Example 1: 2's Complement Conversion
Problem: Find the 8-bit 2's complement binary representation of the decimal integer − 43 10 -43_{10} − 4 3 10 .
Solution:
Write positive magnitude + 43 10 +43_{10} + 4 3 10 in 8-bit binary: + 43 10 = 00101011 2 +43_{10} = 00101011_2 + 4 3 10 = 0010101 1 2
Take the 1's complement (invert all bits): 1’s Comp = 11010100 2 \text{1's Comp} = 11010100_2 1’s Comp = 1101010 0 2
Add 1 to obtain 2's complement: 2’s Comp = 11010100 2 + 1 2 = 11010101 2 \text{2's Comp} = 11010100_2 + 1_2 = 11010101_2 2’s Comp = 1101010 0 2 + 1 2 = 1101010 1 2 Thus, − 43 10 = 11010101 2 -43_{10} = 11010101_2 − 4 3 10 = 1101010 1 2 .
Example 2: Boolean Expression Simplification
Problem: Simplify the Boolean expression Y = A B C + A B C ˉ + A B ˉ C Y = A B C + A B \bar{C} + A \bar{B} C Y = A BC + A B C ˉ + A B ˉ C .
Solution:
Factor out A B AB A B from the first two terms: Y = A B ( C + C ˉ ) + A B ˉ C Y = A B (C + \bar{C}) + A \bar{B} C Y = A B ( C + C ˉ ) + A B ˉ C
Apply inverse law C + C ˉ = 1 C + \bar{C} = 1 C + C ˉ = 1 : Y = A B ( 1 ) + A B ˉ C = A B + A B ˉ C Y = A B (1) + A \bar{B} C = A B + A \bar{B} C Y = A B ( 1 ) + A B ˉ C = A B + A B ˉ C
Factor out A A A from remaining terms: Y = A ( B + B ˉ C ) Y = A (B + \bar{B} C) Y = A ( B + B ˉ C )
Apply distributive law B + B ˉ C = ( B + B ˉ ) ( B + C ) = 1 ⋅ ( B + C ) B + \bar{B} C = (B + \bar{B})(B + C) = 1 \cdot (B + C) B + B ˉ C = ( B + B ˉ ) ( B + C ) = 1 ⋅ ( B + C ) : Y = A ( B + C ) = A B + A C Y = A (B + C) = A B + A C Y = A ( B + C ) = A B + A C