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7.4 Logic Circuits, Switching Theory & Microprocessor Systems
PRC Registered Electrical Engineer REE
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7.4 Logic Circuits, Switching Theory & Microprocessor Systems
Key Takeaways Explain This Topic AI
Enhanced TOS topic C of ESAS bundles Computer Programming, Microprocessor Systems, and Logic Circuits & Switching Theory into 4.5% of the exam and 15 of the 100 ESAS items.
A Karnaugh map minimises a Boolean function by grouping adjacent 1-cells in powers of two; each group of 2^k cells eliminates k variables from that product term.
NAND and NOR are functionally complete gates — any Boolean function can be built from either alone, which is why real silicon is NAND-dominated.
A latch is level-sensitive while a flip-flop is edge-triggered; n cascaded flip-flops form a ripple counter with 2^n states.
A microprocessor executes the fetch-decode-execute cycle over address, data and control buses; an n-bit address bus can address 2^n distinct memory locations.
Last updated: August 2026
7.4 Logic Circuits, Switching Theory & Microprocessor Systems
Topic C of the Engineering Sciences and Allied Subjects TOS (PRBEE Resolution No. 40, s. 2024 ) is Computer Programming, Microprocessor Systems and Logic Circuits and Switching Theory , weighted 4.5% of the whole examination and 15 of the 100 ESAS items — one of the two largest ESAS topics. The preceding section covered number systems, Boolean algebra fundamentals and structured programming; this section completes the topic with switching-theory minimisation, sequential logic and microprocessor architecture, all of which underpin the PLC and protection-relay logic examined in the professional subject.
- 1. Switching Theory & Boolean Minimisation
- De Morgan's Theorems
The two identities that convert between AND and OR forms, and the basis of "bubble pushing": A ⋅ B ‾ = A ‾ + B ‾ A + B ‾ = A ‾ ⋅ B ‾ \overline{A \cdot B} = \overline{A} + \overline{B} \qquad\qquad \overline{A + B} = \overline{A} \cdot \overline{B} A ⋅ B = A + B A + B = A ⋅ B
- Canonical Forms
- Sum of Products (SOP) — an OR of AND terms, one minterm per row where the output is 1;
Product of Sums (POS) — an AND of OR terms, one maxterm per row where the output is 0.
Karnaugh Map Minimisation
A K-map arranges minterms so that physically adjacent cells differ in exactly one variable (Gray-code ordering). Rules:
Group adjacent 1-cells in blocks of 1 , 2 , 4 , 8 , … 1, 2, 4, 8, \dots 1 , 2 , 4 , 8 , … — powers of two only;
- Make each group as large as possible; a group of 2 k 2^k 2 k cells eliminates k k k variables;
- Groups may overlap and may wrap around the edges of the map;
- Every 1-cell must be covered at least once; use the fewest groups possible;
Don't-care cells ( X X X ) may be included in a group when doing so enlarges it, or ignored otherwise.
Universal Gates
- Gate Expression Notes
- AND Y = A B Y = AB Y = A B Output 1 only when all inputs are 1
- OR Y = A + B Y = A + B Y = A + B Output 1 when any input is 1
- NAND Y = A B ‾ Y = \overline{AB} Y = A B Functionally complete
- NOR Y = A + B ‾ Y = \overline{A+B} Y = A + B Functionally complete
XOR Y = A ⊕ B = A B ‾ + A ‾ B Y = A \oplus B = A\overline{B} + \overline{A}B Y = A ⊕ B = A B + A B Output 1 when inputs differ; the parity/half-adder sum gate
XNOR Y = A ⊕ B ‾ Y = \overline{A \oplus B} Y = A ⊕ B Output 1 when inputs agree; the equality comparator
NAND and NOR are each functionally complete : NOT, AND and OR can all be synthesised from either alone. Because a CMOS NAND is cheaper in silicon than an AND, real integrated logic is overwhelmingly NAND-based.
2. Combinational Logic Blocks
- Block Function Sizing rule
- Half adder Sum = A ⊕ B = A \oplus B = A ⊕ B , Carry = A B = AB = A B No carry-in
Full adder Sum = A ⊕ B ⊕ C i n = A \oplus B \oplus C_{in} = A ⊕ B ⊕ C in , C o u t = A B + C i n ( A ⊕ B ) C_{out} = AB + C_{in}(A \oplus B) C o u t = A B + C in ( A ⊕ B ) Cascade n n n for an n n n -bit ripple adder
- Multiplexer (MUX) Selects 1 of 2 n 2^n 2 n inputs n n n select lines
- Demultiplexer Routes 1 input to 1 of 2 n 2^n 2 n outputs n n n select lines
- Decoder n n n inputs drive 2 n 2^n 2 n mutually exclusive outputs Address decoding
- Encoder 2 n 2^n 2 n inputs produce an n n n -bit code Priority encoders resolve simultaneous inputs
- 3. Sequential Logic
The defining distinction: combinational output depends only on present inputs; sequential output depends on present inputs and stored state.
- Element Behaviour Characteristic equation
- SR latch Set/Reset; S = R = 1 S = R = 1 S = R = 1 is forbidden —
- D flip-flop Output follows D at the clock edge Q n e x t = D Q_{next} = D Q n e x t = D
JK flip-flop J = K = 1 J=K=1 J = K = 1 toggles — no forbidden state Q n e x t = J Q ‾ + K ‾ Q Q_{next} = J\overline{Q} + \overline{K}Q Q n e x t = J Q + K Q
T flip-flop Toggles when T = 1 T = 1 T = 1 Q n e x t = T ⊕ Q Q_{next} = T \oplus Q Q n e x t = T ⊕ Q
A latch is level-sensitive (transparent while the enable is asserted); a flip-flop is edge-triggered. Confusing the two is a standard distractor.
Cascading n n n flip-flops produces a counter with 2 n 2^n 2 n states, so a 4-bit counter counts 0–15 and a modulo-10 (decade) counter needs 4 flip-flops with a reset decoded at count 10. A shift register of n n n stages delays serial data by n n n clock periods.
Finite state machines come in two flavours: a Moore machine's output depends on the state only; a Mealy machine's output depends on state and current input, so it reacts one clock earlier but is more prone to output glitches.
4. Microprocessor Systems
A microprocessor repeats the fetch–decode–execute cycle across three buses:
Address bus — unidirectional, sets the location; n n n address lines address 2 n 2^n 2 n locations, so 16 lines reach 64 Ki locations and 20 lines reach 1 Mi;
Data bus — bidirectional, carries the operand; its width defines the machine's word size;
Control bus — read/write strobes, interrupt requests, clock and reset. Addressable memory = 2 ( number of address lines ) locations \text{Addressable memory} = 2^{(\text{number of address lines})} \text{ locations} Addressable memory = 2 ( number of address lines ) locations
Key architectural distinctions for the examination:
- Contrast Von Neumann Harvard
- Memory Shared program and data memory Separate program and data memories
- Bottleneck Single bus limits throughput Simultaneous instruction and data fetch
- Typical use General-purpose processors DSPs, most microcontrollers, PLC processors
Microprocessor vs. microcontroller: a microprocessor is a CPU requiring external memory and peripherals; a microcontroller integrates CPU, RAM, ROM/flash, timers and I/O on a single chip — the architecture inside a protective relay, a variable-frequency drive controller or a smart meter.
Interrupts suspend the running program, save the context, execute an interrupt service routine and return. Maskable interrupts can be disabled in software; non-maskable interrupts (used for power-fail detection in substation IEDs) cannot. Polling , by contrast, wastes processor time continuously checking a flag.
- Solved Board Exam Examples
- Example 1: Boolean Simplification
Simplify Y = A B ‾ + A B + A ‾ B Y = A\overline{B} + AB + \overline{A}B Y = A B + A B + A B .
Solution. Combine the first two terms, which differ only in B B B : A B ‾ + A B = A ( B ‾ + B ) = A ( 1 ) = A A\overline{B} + AB = A(\overline{B} + B) = A(1) = A A B + A B = A ( B + B ) = A ( 1 ) = A Y = A + A ‾ B Y = A + \overline{A}B Y = A + A B
Applying the absorption identity X + X ‾ Y = X + Y X + \overline{X}Y = X + Y X + X Y = X + Y : Y = A + B Y = \boxed{A + B} Y = A + B
The function is simply OR — three product terms collapse to one two-input gate.
Example 2: Address Bus Sizing
A microcontroller must address 256 KiB of memory. How many address lines are required?
Solution. 256 KiB = 256 × 1024 = 262 144 = 2 18 256 \text{ KiB} = 256 \times 1024 = 262\,144 = 2^{18} 256 KiB = 256 × 1024 = 262 144 = 2 18 bytes. n = log 2 ( 2 18 ) = 18 address lines n = \log_{2}(2^{18}) = \boxed{18 \text{ address lines}} n = lo g 2 ( 2 18 ) = 18 address lines
Sixteen lines would reach only 64 KiB, and 20 lines would reach 1 MiB — both are supplied as distractors.
Example 3: Decade Counter Flip-Flop Count
How many flip-flops are needed for a modulo-10 (BCD decade) counter?
Solution. The counter must represent ten distinct states, 0 through 9, so we need the smallest n n n satisfying 2 n ≥ 10 2^n \ge 10 2 n ≥ 10 . Since 2 3 = 8 < 10 2^3 = 8 < 10 2 3 = 8 < 10 and 2 4 = 16 ≥ 10 2^4 = 16 \ge 10 2 4 = 16 ≥ 10 , the answer is 4 flip-flops \boxed{4 \text{ flip-flops}} 4 flip-flops , with the unused states 10–15 decoded to force a synchronous reset back to zero.