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9.3 Sequential Logic, Flip-Flops & Microprocessor Architecture

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PRC Electronics Engineering Licensure Examination Study Guide Exam

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1 Chapter 1: Introduction & Board Exam Strategy

1.1 PRC ECE Licensure Exam Overview & Regulation 1.2 Table of Specifications & Exam Strategy

2 Chapter 2: Mathematics Foundations

2.1 College & Advanced Algebra 2.2 Trigonometry & Solid Mensuration 2.3 Analytic Geometry & Differential Calculus 2.4 Integral Calculus & Applications

3 Chapter 3: Advanced Mathematics for ECE

3.1 Differential Equations & Circuit Transients 3.2 Complex Numbers & Laplace Transforms 3.3 Fourier Series, Fourier Transforms & Z-Transforms 3.4 Vector Analysis, Matrices & Probability

4 Chapter 4: GEAS - Engineering Sciences & Economics

4.1 Engineering Physics & Materials Chemistry 4.2 Engineering Mechanics & Strength of Materials 4.3 Engineering Economics & Financial Analysis 4.4 Computer Fundamentals & C/C++ Programming

5 Chapter 5: GEAS - Management, Materials, Environment & CAD

5.1 Engineering Management & Technopreneurship 101 5.2 Materials Science & Engineering 5.3 Environment Science & Engineering 5.4 Computer-Aided Drawing (CAD) & Engineering Graphics

6 Chapter 6: GEAS - ECE Laws, Ethics & Contracts

6.1 Republic Act No. 9292 (Electronics Engineering Law of 2004) 6.2 ECE Code of Ethics & Professional Conduct 6.3 Contracts, Specifications & National Building Code (PD 1096)

7 Chapter 7: Electronics Engineering - Circuits & Semiconductor Diodes

7.1 DC & AC Circuit Analysis & Network Theorems 7.2 Electromagnetics & Passive Components 7.3 Semiconductor Physics & Diode Circuits 7.4 Power Supply Design & Voltage Regulators

8 Chapter 8: Electronics Engineering - Transistors & Analog Circuits

8.1 BJT Operation, Biasing & Small-Signal Amplifiers 8.2 FET Characteristics, Biasing & Amplifier Circuits 8.3 Multistage Amplifiers, Frequency Response & Power Amplifiers 8.4 Operational Amplifiers & Active Filter Design

9 Chapter 9: Electronics Engineering - Digital Electronics & Control Systems

9.1 Feedback Topologies & Oscillator Circuits 9.2 Boolean Algebra, Logic Gates & Combinational Circuits 9.3 Sequential Logic, Flip-Flops & Microprocessor Architecture 9.4 Industrial Power Electronics & Control System Theory

10 Chapter 10: EST - Communications Fundamentals & Transmission Lines

10.1 Signal Fundamentals, Decibel Calculations & Noise Analysis 10.2 Amplitude Modulation (AM) Principles & Receivers 10.3 Frequency Modulation (FM), Phase Modulation & Discriminators 10.4 Transmission Line Parameters, SWR & Smith Chart

11 Chapter 11: EST - Digital Communications, Wireless & Optical Systems

11.1 Pulse & Digital Modulation Systems 11.2 Data Communications, OSI Model & Protocols 11.3 Antenna Principles & Electromagnetic Wave Propagation 11.4 Optical Fiber, Microwave, Satellite & Philippine NTC Regulations

9.3 Sequential Logic, Flip-Flops & Microprocessor Architecture

Key Takeaways Explain This Topic AI

Sequential logic circuits incorporate memory elements where output states depend on both present inputs and past state history, governed by clock synchronization.

The JK flip-flop eliminates the invalid state of SR flip-flops; when J=1 and K=1, the output toggles to its complement (Q_{next} = NOT(Q)) upon receiving a clock edge.

Counters constructed from n cascaded flip-flops have a maximum modulus of MOD = 2ⁿ; truncated MOD-N counters utilize logic feedback to clear flip-flops upon reaching count N.

The Intel 8085 microprocessor features an 8-bit data bus and 16-bit address bus (64 KB address space), whereas the Intel 8086 provides a 16-bit data bus and 20-bit address bus capable of addressing 1 MB across segmented memory blocks.

Memory address decoding uses high-order address lines routed through decoder ICs (such as 74LS138) to generate Chip Select (NOT(CS)) signals that map RAM/ROM into non-overlapping memory regions.

Last updated: July 2026

9.3 Sequential Logic, Flip-Flops & Microprocessor Architecture

Quick Answer: Sequential logic circuits rely on memory elements (flip-flops) where current output depends on present inputs and previous internal state. The JK flip-flop toggles (Q_{next} = NOT(Q)) when J=K=1, solving the SR invalid state. n-bit counters achieve a maximum modulus MOD = 2ⁿ. Microprocessor systems use unidirectional address buses, bidirectional data buses, and control buses to interface with memory and I/O. The 8-bit Intel 8085 addresses 64 KB (16-bit address bus), while the 16-bit Intel 8086 uses a 20-bit address bus to access 1 MB of segmented memory decoded via address decoders like the 74LS138.

1. Latches vs. Flip-Flops & Excitation Characteristics

Unlike combinational logic, sequential logic circuits contain memory elements. A latch is an asynchronous level-sensitive storage element, whereas a flip-flop is a clock-edge-triggered bistable multivibrator.

Primary Flip-Flop Types & Characteristic Equations

SR (Set-Reset) Flip-Flop:

Characteristic Equation: Q_{next} = S + NOT(R)Q (Condition: S · R = 0)

Invalid State: S=1, R=1 results in unpredictable output states and must be prohibited.

JK Flip-Flop:

Characteristic Equation: Q_{next} = J NOT(Q) + NOT(K)Q

Toggles output (Q_{next} = NOT(Q)) when J=1, K=1. Master-Slave configurations or edge-triggering eliminate race-around conditions when clock pulse width exceeds flip-flop propagation delay.

D (Data/Delay) Flip-Flop:

Characteristic Equation: Q_{next} = D

Formed by connecting J=D and K=NOT(D) on a JK flip-flop. Transfers input D to output Q on the active clock edge.

T (Toggle) Flip-Flop:

Characteristic Equation: Q_{next} = T ⊕ Q = T NOT(Q) + NOT(T)Q

Formed by tying J=K=T. Toggles when T=1, holds state when T=0. Used extensively in binary frequency division and counters.

Flip-Flop Excitation Table

The excitation table dictates the required input conditions to force a transition from present state Q to next state Q_{next}:

  • Present State Q Next State Q_{next} S R J K D T
  • 0 0 0 X 0 X 0 0
  • 0 1 1 0 1 X 1 1
  • 1 0 0 1 X 1 0 1
  • 1 1 X 0 X 0 1 0

(X represents a Don't Care condition).

Timing Constraints

Setup Time (t_{su}): Minimum duration input signals must remain stable before the active clock edge.

Hold Time (t_h): Minimum duration input signals must remain stable after the active clock edge.

  • 2. Counters & Shift Registers
  • Asynchronous (Ripple) vs. Synchronous Counters

Asynchronous (Ripple) Counters: The output of each flip-flop drives the clock input of the next stage. Ripple counters suffer from accumulated propagation delay (t_{total} = n · t_{pd}), limiting maximum operating frequency.

Synchronous Counters: All flip-flops are tied to a common global clock signal, triggering simultaneously. Logic gates determine next-state excitation, eliminating ripple accumulation.

Counter Modulus & Mod-N Design

The Modulus (MOD) of a counter is the total number of unique states it cycles through before repeating.

An n-bit binary counter has a maximum modulus of MOD = 2ⁿ.

Truncated MOD-N Counters: To design a counter with MOD = N < 2ⁿ, a NAND gate detects count N in binary and asserts active-low asynchronous NOT(CLEAR) inputs on all flip-flops, resetting the count to 0.

Shift Register Classifications

Shift registers consist of cascaded D or JK flip-flops that move data bits by one position per clock pulse.

SISO (Serial-In, Serial-Out): Converts serial data into delayed serial data.

SIPO (Serial-In, Parallel-Out): Converts serial input into n-bit parallel data words.

PISO (Parallel-In, Serial-Out): Loads n-bit parallel data simultaneously and shifts out serially.

PIPO (Parallel-In, Parallel-Out): Functions as a multi-bit memory buffer register.

Special Shift Counters:

Ring Counter: Connects the output of the last flip-flop directly to the first (Q_n → D₀). An n-bit Ring counter has N = n states.

Johnson (Twisted Ring) Counter: Connects inverted output of last flip-flop to first (NOT(Q_n) → D₀). An n-bit Johnson counter yields N = 2n states.

  • 3. Microprocessor Architecture: Intel 8085 & 8086
  • Bus Structure Principles

Microprocessor systems communicate with memory and peripheral devices over three primary system buses:

Address Bus: Unidirectional. Carries memory or I/O address location coordinates from CPU to external chips.

Data Bus: Bidirectional. Transfers instructions and data between CPU, memory, and peripheral devices.

Control Bus: Contains individual control lines (NOT(RD), NOT(WR), M/NOT(IO), ALE) that dictate timing and operation direction. +-------------------------------------------------+

  • | Intel Microprocessor (CPU) |
  • +-------+-------------------+-----------------+---+
  • | | |
  • Address Bus | (Unidirectional) | Data Bus | Control Bus
  • =============> <=================> =============>
  • | | |
  • +-------v-------------------v-----------------v---+
  • | System Memory (SRAM / DRAM / EPROM) |
  • +-------------------------------------------------+
  • Intel 8085 Microprocessor (8-bit)

Data Bus Width: 8 bits (D₀ - D₇).

Address Bus Width: 16 bits (A₀ - A₁₅), providing an addressable memory range of 2¹⁶ = 65,536 bytes (64 KB). Lower address lines are multiplexed with data lines (AD₀ - AD₇) to save pin count, demultiplexed using an external latch (74LS373) triggered by Address Latch Enable (ALE) .

Internal Registers: Accumulator (A), Flags, general-purpose registers (B, C, D, E, H, L paired as BC, DE, HL), 16-bit Program Counter (PC), and 16-bit Stack Pointer (SP).

Intel 8086 Microprocessor (16-bit)

Data Bus Width: 16 bits (D₀ - D₁₅).

Address Bus Width: 20 bits (A₀ - A₁₉), expanding addressable physical memory to 2²⁰ = 1,048,576 bytes (1 MB).

Internal Architecture: Divided into two parallel processing units:

Bus Interface Unit (BIU): Fetches instructions, handles memory address calculations, and maintains a 6-byte instruction prefetch queue.

Execution Unit (EU): Decodes and executes instructions using the 16-bit ALU and register set.

Memory Segmentation: The 1 MB memory space is divided into logical segments of 64 KB each. Physical addresses are computed by shifting a 16-bit Segment Register left by 4 bits (16₁₀) and adding a 16-bit Offset Register: Physical Address = ( Segment Register × 16 10 ) + Offset \text{Physical Address} = (\text{Segment Register} \times 16_{10}) + \text{Offset} Physical Address = ( Segment Register × 1 6 10 ​ ) + Offset

Code Segment (CS:IP), Data Segment (DS:SI), Stack Segment (SS:SP), Extra Segment (ES:DI).

4. Memory Systems & Address Decoding

Computer memory consists of Read-Only Memory (ROM - non-volatile instruction storage) and Random-Access Memory (RAM - volatile read/write workspace).

Address Decoding Techniques

To prevent memory bus contention, each memory IC is assigned a unique address range using decoding circuitry to activate the chip's active-low Chip Select (NOT(CS)) or Chip Enable (NOT(CE)) input.

High-order address lines (A₁₅-A₁₃ in 8085) connect to decoder inputs (e.g., 3-to-8 Decoder 74LS138), while low-order address lines (A₁₂-A₀) connect directly to memory IC address pins.

Example Calculation: Connecting A₁₅, A₁₄, A₁₃ to a 74LS138 decoder divides 64 KB into eight 8 KB blocks (8192 bytes per NOT(CS) output). Output NOT(Y₀) activates for address range 0000H to 1FFFH, NOT(Y₁) for 2000H to 3FFFH, and so forth.