Study guide
8.2 FET Characteristics, Biasing & Amplifier Circuits
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8.1 BJT Operation, Biasing & Small-Signal Amplifiers 8.2 FET Characteristics, Biasing & Amplifier Circuits 8.3 Multistage Amplifiers, Frequency Response & Power Amplifiers 8.4 Operational Amplifiers & Active Filter Design
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8.2 FET Characteristics, Biasing & Amplifier Circuits
Key Takeaways Explain This Topic AI
Field-Effect Transistors (FETs) are unipolar, voltage-controlled devices with high input impedance ( 10 8 10^8 1 0 8 to 10 14 Ω 10^{14} \Omega 1 0 14 Ω ) drawing virtually zero gate current ( I G ≈ 0 I_G \approx 0 I G ≈ 0 ).
JFETs and Depletion MOSFETs (D-MOSFETs) follow Shockley's equation in saturation: I D = I D S S ( 1 − V G S V P ) 2 I_D = I_{DSS}\left(1 - \frac{V_{GS}}{V_P}\right)^2 I D = I D SS ( 1 − V P V GS ) 2 , where V P V_P V P is the pinch-off voltage and I D S S I_{DSS} I D SS is drain saturation current at V G S = 0 V_{GS} = 0 V GS = 0 .
Enhancement MOSFETs (E-MOSFETs) operate purely above threshold voltage V_{Th} according to I_D = k(V_{GS} - V_{Th})^2.
FET transconductance is defined as g m = ∂ I D ∂ V G S g_m = \frac{\partial I_D}{\partial V_{GS}} g m = ∂ V GS ∂ I D ; for JFETs, g m = g m 0 ( 1 − V G S V P ) = 2 I D S S I D ∣ V P ∣ g_m = g_{m0}\left(1 - \frac{V_{GS}}{V_P}\right) = \frac{2 \sqrt{I_{DSS} I_D}}{|V_P|} g m = g m 0 ( 1 − V P V GS ) = ∣ V P ∣ 2 I D SS I D , where g m 0 = 2 I D S S ∣ V P ∣ g_{m0} = \frac{2 I_{DSS}}{|V_P|} g m 0 = ∣ V P ∣ 2 I D SS .
Common Source (CS) amplifiers deliver high voltage gain with 180° phase inversion; Common Drain (CD / Source Follower) offers high Z_in, low Z_out, and near-unity voltage gain; Common Gate (CG) offers low Z_in, high voltage gain, and zero phase shift.
Last updated: July 2026
- 8.2 FET Characteristics, Biasing & Amplifier Circuits
- 1. FET Physical Fundamentals & Device Classification
Field-Effect Transistors (FETs) are voltage-controlled , unipolar semiconductor devices in which conduction occurs purely via majority charge carriers (electrons in N-channel, holes in P-channel). Because the gate terminal is reverse-biased or insulated by silicon dioxide ( S i O 2 SiO_2 S i O 2 ), input impedance is extremely high ( 10 8 Ω 10^8\ \Omega 1 0 8 Ω for JFETs, up to 10 14 Ω 10^{14}\ \Omega 1 0 14 Ω for MOSFETs).
Classification of Field-Effect Transistors
Junction Field-Effect Transistors (JFET): Reverse-biased p n pn p n junction controls depletion region width and channel cross-sectional area.
Depletion-Mode MOSFET (D-MOSFET): Built with a physical channel; can operate in depletion mode ( V G S < 0 V_{GS} < 0 V GS < 0 ) or enhancement mode ( V G S > 0 V_{GS} > 0 V GS > 0 ).
Enhancement-Mode MOSFET (E-MOSFET): No physical channel at V G S = 0 V V_{GS} = 0\text{ V} V GS = 0 V . An inversion layer channel is induced when V G S V_{GS} V GS exceeds threshold voltage V T h V_{Th} V T h .
BJT vs. FET Comparison
Characteristic BJT (Bipolar Junction Transistor) FET (Field-Effect Transistor)
Control Mechanism Current-Controlled ( I C = β I B I_C = \beta I_B I C = β I B ) Voltage-Controlled ( I D = f ( V G S ) I_D = f(V_{GS}) I D = f ( V GS ) )
Carriers Bipolar (Majority & Minority) Unipolar (Majority only)
Input Impedance ( Z i n Z_{in} Z in ) Moderate ( 1 k Ω − 10 k Ω 1\text{ k}\Omega - 10\text{ k}\Omega 1 k Ω − 10 k Ω ) Extremely High ( 10 8 − 10 14 Ω 10^8 - 10^{14}\ \Omega 1 0 8 − 1 0 14 Ω )
- Noise Performance Moderately Noisy Low Noise (ideal for RF front-ends)
- Thermal Stability Negative temp coefficient (Thermal Runaway risk) Positive temp coefficient (Self-limiting)
- Gain Parameter Current gain β \beta β or h f e h_{fe} h f e Transconductance g m g_m g m
- 2. FET Transfer Characteristics & Mathematical Equations
- A. Shockley's Equation (JFET & D-MOSFET)
In the saturation (pinch-off/active) region where V D S ≥ ∣ V G S − V P ∣ V_{DS} \ge |V_{GS} - V_P| V D S ≥ ∣ V GS − V P ∣ : I D = I D S S ( 1 − V G S V P ) 2 I_D = I_{DSS} \left( 1 - \frac{V_{GS}}{V_P} \right)^2 I D = I D SS ( 1 − V P V GS ) 2
Where:
I D S S I_{DSS} I D SS : Drain-to-source saturation current when V G S = 0 V V_{GS} = 0\text{ V} V GS = 0 V .
V P V_P V P (or V G S ( o f f ) V_{GS(off)} V GS ( o ff ) ): Pinch-off voltage at which I D = 0 A I_D = 0\text{ A} I D = 0 A . For N-channel JFET, V P V_P V P is negative.
B. E-MOSFET Saturation Current Equation
For V G S > V T h V_{GS} > V_{Th} V GS > V T h and V D S ≥ V G S − V T h V_{DS} \ge V_{GS} - V_{Th} V D S ≥ V GS − V T h : I D = k ( V G S − V T h ) 2 I_D = k (V_{GS} - V_{Th})^2 I D = k ( V GS − V T h ) 2
Where constant k k k is given by: k = I D ( o n ) ( V G S ( o n ) − V T h ) 2 = 1 2 μ n C o x ( W L ) k = \frac{I_{D(on)}}{(V_{GS(on)} - V_{Th})^2} = \frac{1}{2} \mu_n C_{ox} \left(\frac{W}{L}\right) k = ( V GS ( o n ) − V T h ) 2 I D ( o n ) = 2 1 μ n C o x ( L W )
C. Transconductance ( g m g_m g m )
Transconductance quantifies the control of gate voltage over drain current: g m = ∂ I D ∂ V G S g_m = \frac{\partial I_D}{\partial V_{GS}} g m = ∂ V GS ∂ I D
For JFETs & D-MOSFETs: g m = g m 0 ( 1 − V G S V P ) = 2 I D S S I D ∣ V P ∣ g_m = g_{m0} \left( 1 - \frac{V_{GS}}{V_P} \right) = \frac{2 \sqrt{I_{DSS} I_D}}{|V_P|} g m = g m 0 ( 1 − V P V GS ) = ∣ V P ∣ 2 I D SS I D
Where maximum transconductance at V G S = 0 V V_{GS} = 0\text{ V} V GS = 0 V is: g m 0 = 2 I D S S ∣ V P ∣ g_{m0} = \frac{2 I_{DSS}}{|V_P|} g m 0 = ∣ V P ∣ 2 I D SS
For E-MOSFETs: g m = 2 k ( V G S − V T h ) = 2 k I D g_m = 2 k (V_{GS} - V_{Th}) = 2 \sqrt{k I_D} g m = 2 k ( V GS − V T h ) = 2 k I D
- 3. FET DC Biasing Circuits
- A. Self-Bias Circuit (JFET & D-MOSFET)
Gate is referenced to ground via high resistor R G R_G R G ( I G = 0 A ⟹ V G = 0 V I_G = 0\text{ A} \implies V_G = 0\text{ V} I G = 0 A ⟹ V G = 0 V ).
Gate-Source Bias Voltage: V G S = − I D R S V_{GS} = -I_D R_S V GS = − I D R S
Combining with Shockley's equation yields a quadratic equation in I D I_D I D : I D = I D S S ( 1 + I D R S V P ) 2 I_D = I_{DSS} \left( 1 + \frac{I_D R_S}{V_P} \right)^2 I D = I D SS ( 1 + V P I D R S ) 2
Drain-Source Voltage: V D S = V D D − I D ( R D + R S ) V_{DS} = V_{DD} - I_D(R_D + R_S) V D S = V DD − I D ( R D + R S )
B. Voltage-Divider Bias Circuit
Gate Voltage: V G = V D D ⋅ R 2 R 1 + R 2 V_G = V_{DD} \cdot \frac{R_2}{R_1 + R_2} V G = V DD ⋅ R 1 + R 2 R 2
Gate-Source Voltage: V G S = V G − I D R S V_{GS} = V_G - I_D R_S V GS = V G − I D R S
Solved algebraically or graphically by intersecting the bias line V G S = V G − I D R S V_{GS} = V_G - I_D R_S V GS = V G − I D R S with the Shockley transfer curve.
C. Drain-Feedback Bias (E-MOSFET)
Resistor R G R_G R G connected between Drain and Gate ( I G = 0 ⟹ V G S = V D S I_G = 0 \implies V_{GS} = V_{DS} I G = 0 ⟹ V GS = V D S ): V G S = V D S = V D D − I D R D V_{GS} = V_{DS} = V_{DD} - I_D R_D V GS = V D S = V DD − I D R D
4. Small-Signal AC FET Amplifiers
In AC equivalent models, the FET is modeled as a voltage-controlled current source g m v g s g_m v_{gs} g m v g s in parallel with drain resistance r d = 1 y o s r_d = \frac{1}{y_{os}} r d = y os 1 .
- A. Common Source (CS) Amplifier (Bypassed R S R_S R S )
- Input Impedance: Z i n = R G Z_{in} = R_G Z in = R G
Output Impedance: Z o u t = R D ∥ r d ≈ R D Z_{out} = R_D \parallel r_d \approx R_D Z o u t = R D ∥ r d ≈ R D
No-Load Voltage Gain: A v = − g m ( R D ∥ r d ) ≈ − g m R D A_v = -g_m (R_D \parallel r_d) \approx -g_m R_D A v = − g m ( R D ∥ r d ) ≈ − g m R D
Loaded Voltage Gain: A v L = − g m ( R D ∥ R L ) A_{vL} = -g_m (R_D \parallel R_L) A vL = − g m ( R D ∥ R L )
Phase Relationship: 180 ∘ 180^\circ 18 0 ∘ phase inversion.
B. Common Source with Unbypassed Source Resistor ( R S R_S R S )
Voltage Gain: A v = − g m ( R D ∥ R L ) 1 + g m R S A_v = -\frac{g_m (R_D \parallel R_L)}{1 + g_m R_S} A v = − 1 + g m R S g m ( R D ∥ R L )
Benefit: Degenerative feedback stabilizes gain against g m g_m g m variations.
- C. Common Drain (CD) / Source Follower
- Input Impedance: Z i n = R G Z_{in} = R_G Z in = R G
- Output Impedance: Z o u t = R S ∥ 1 g m Z_{out} = R_S \parallel \frac{1}{g_m} Z o u t = R S ∥ g m 1
Voltage Gain: A v = g m ( R S ∥ R L ) 1 + g m ( R S ∥ R L ) ≈ + 1 A_v = \frac{g_m (R_S \parallel R_L)}{1 + g_m (R_S \parallel R_L)} \approx +1 A v = 1 + g m ( R S ∥ R L ) g m ( R S ∥ R L ) ≈ + 1
Phase Relationship: 0 ∘ 0^\circ 0 ∘ phase shift.
Primary Application: High-input impedance buffer.
D. Common Gate (CG) Amplifier
Input Impedance: Z i n = R S ∥ 1 g m ≈ 1 g m Z_{in} = R_S \parallel \frac{1}{g_m} \approx \frac{1}{g_m} Z in = R S ∥ g m 1 ≈ g m 1 (Low, e.g., 100 − 500 Ω 100-500\ \Omega 100 − 500 Ω )
- Output Impedance: Z o u t = R D Z_{out} = R_D Z o u t = R D
- Voltage Gain: A v = + g m ( R D ∥ R L ) A_v = +g_m (R_D \parallel R_L) A v = + g m ( R D ∥ R L )
Phase Relationship: 0 ∘ 0^\circ 0 ∘ phase shift.